參數(shù)資料
型號(hào)： M38C29FFAFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 5 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 23/104頁(yè)
文件大?。?/td> 1327K
代理商： M38C29FFAFP
Rev.2.00
May 28, 2004
page 23 of 100
38C2 Group (A Version)
TIMERS
8-Bit Timer
The 38C2 group has four built-in timers : Timer 1, Timer 2, Timer 3,
and Timer 4.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “0016”, the contents of the timer latch is
reloaded into the timer with the next count pulse. In this mode, the
interrupt request bit corresponding to that timer is set to “ 1” .
The count can be stopped by setting the stop bit of each timer to “1”.
q Frequency Divider For Timer
Timer 1, timer 2, timer 3 and timer 4 have the frequency divider for
the count source. The count source of the frequency divider is switched
to XIN or XCIN by the CPU mode register. The frequency divider is
controlled by each timer division ratio selection bit. The division ratio
can be selected from as follows;
1/1, 1/2, 1/16, 1/32, 1/64, 1/128, 1/256, 1/1024 of f(XIN); or f(XCIN).
q Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register.
When f(XCIN) is selected as the count source, counting can be per-
formed regardless of XCIN oscillation. However, when XCIN is stopped,
the external pulse input from XCIN pin is counted. Also, by the timer
12 mode register, each time timer 2 underflows, the signal of which
polarity is inverted can be output from P36/T2OUT pin.
At reset, all bits of the timer 12 mode register are set to “0,” timer 1 is
set to “FF16”, and timer 2 is set to “0116”.
When executing the STP instruction, previously set the wait time at
return.
q Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. Also, by the timer 34 mode register, each
time timer 3 or timer 4 underflows, the signal of which polarity is
inverted can be output from P52/T3OUT pin or P53/T4OUT pin.
q Timer 3 PWM0 Mode, Timer 4 PWM1 Mode
A PWM rectangular waveform corresponding to the 10-bit accuracy
can be output from the P52/PWM0 pin and P53/PWM1 pin by set-
ting the timer 34 mode register and PWM01 register (refer to Figure
21).
One output pulse is the short interval. Four output pulses are the
long interval. The “n” is the value set in the timer 3 (address 002216)
or the timer 4 (address 002316). The “ts” is one period of timer 3 or
timer 4 count source. “H” width of the short interval is obtained by n
ts.
However, in the long interval, “H” width of output pulse is extended
for ts which is set by the PWM01 register (address 002416).
s Notes on Timer 3 PWM0 Mode, Timer 4 PWM1
Mode
qWhen PWM output is suspended after starting PWM output, de-
pending on the level of the output pulse at that time to resume an
output, the delay of the one section of the short interval may be
needed.
Stop at “ H” : No output delay
Stop at “ L” : Output is delayed time of 256
ts
qIn the PWM mode, the follows are performed every cycle of the
long interval (4 256 ts).
Generation of timer 3, timer 4 interrupt requests
Update of timer 3, timer 4
s Writing to Timer 2, Timer 3, Timer 4
When writing to the latch only, if the write timing to the reload latch
and the underflow timing are almost the same, the value is set into
the timer and the timer latch at the same time. In this time, counting
is stopped during writing to the reload latch.
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M38C29FFHP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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