參數(shù)資料
型號(hào)： M38C29FFAFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 5 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 20/104頁(yè)
文件大?。?/td> 1327K
代理商： M38C29FFAFP
Rev.2.00
May 28, 2004
page 20 of 100
38C2 Group (A Version)
Fig. 15 Interrupt control
Fig. 16 Structure of interrupt-related registers
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
b7
b0
Interrupt edge selection register
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
INT2/Key input interrupt switch bit
Timer Y/CNTR1 interrupt switch bit
Not used (return “ 0”
when read)
(Do not write to “ 1” )
(INTEDGE : address 003A16)
Interrupt request register 1
INT0 interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
Key input interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Serial I/O2 receive interrupt request bit
Serial I/O2 transmit interrupt request bit
Timer X interrupt request bit
Interrupt control register 1
INT0 interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
Key input interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Serial I/O2 receive interrupt enable bit
Serial I/O2 transmit interrupt enable bit
Timer X interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C16)
(ICON1 : address 003E16)
Interrupt request register 2
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
CNTR0 interrupt request bit
Timer Y interrupt request bit
CNTR1 interrupt request bit
AD conversion interrupt request bit
Not used (returns “ 0”
when read)
(IREQ2 : address 003D16)
Interrupt control register 2
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
CNTR0 interrupt enable bit
Timer Y interrupt enable bit
CNTR1 interrupt enable bit
AD conversion interrupt enable bit
Not used (returns “ 0”
when read)
(Do not write to “ 1” .)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F16)
0 : Falling edge active
1 : Rising edge active
b7
b0
b7
b0
b7
b0
b7
b0
0 : INT2 interrupt
1 : Key input interrupt
0 : Timer Y interrupt
1 : CNTR1 interrupt
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參數(shù)描述
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