參數(shù)資料
型號: M38C29FFAFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 5 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 33/104頁
文件大小: 1327K
代理商: M38C29FFAFP
Rev.2.00
May 28, 2004
page 32 of 100
38C2 Group (A Version)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by set-
ting the serial I/O mode selection bit of the serial I/O control register
to “ 0” .
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift regis-
ter cannot be written to or read from directly, transmit data is written
to the transmit buffer register, and receive data is read from the re-
ceive buffer register.
The transmit buffer register can also hold the next data to be trans-
mitted, and the receive buffer register can hold a character while the
next character is being received.
Fig. 27 Block diagram of UART serial I/O
f(XIN)
1/4
OE
PE FE
1/16
Data bus
Receive buffer register
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Frequency division ratio 1/(n+1)
ST/SP/PA generator
Transmit buffer register
Data bus
Transmit shift register
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
ST detector
SP detector
UART control register
Address 0FE116
[Address 0FE416]
Character length selection bit
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O control register
Serial I/O status register
(f(XCIN) in low-speed mode)
P56/SCLK1
[P31/SCLK2]
P54/RXD1
[P33/RXD2]
P55/TXD1
[P32/TXD2]
Address 001C16
[Address 001E16]
Address 0FE216 [Address 0FE516]
Address 001C16
[Address 001E16]
Address 001D16
[Address 001F16]
Address 0FE016
[Address 0FE316]
[ ] : For Serial I/O2
Fig. 28 Operation of UART serial I/O function
TSC=0
TBE=1
RBF=0
TBE=0TBE=0
RBF=1
ST
D0
D1
SP
D0
D1
ST
SP
TBE=1
TSC=1
ST
D0
D1
SP
D0
D1
ST
SP
Transmit or receive clock
Transmit buffer register
write signal
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC flag =“1”, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC flag = “0”.
Notes
Serial output TXD
Serial input RXD
Receive buffer register
read signal
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