SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
22
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
(1) Timer mode
The timer counts the followings;
f(X
IN
) (input frequency to X
IN
pin) divided by 16 in middle-, or
high-speed mode
f(X
CIN
) (sub-clock oscillation frequency) divided by 16 in low-
speed mode
f(XR
OSC
) (built-in ring oscillator oscillation frequency) divided by
16 in ring oscillator mode
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR
0
pin is inverted and f(X
IN
), f(R
OSC
) or f(X
CIN
) can be selected for
the count source. Except for them, the operation in pulse output
mode is the same as in timer mode. When using a timer in this
mode, set the corresponding port P5
2
direction register to output
mode.
(3) Event counter mode
The timer counts signals input through the CNTR
0
pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P5
2
direction register to input mode.
(4) Pulse width measurement mode
The count source is f(X
IN
)/16 in the middle-, or high-speed mode,
f(R
OSC
)/16 in ring oscillator mode, and f(X
CIN
)/16 in the low-speed
mode. If CNTR
0
active edge switch bit is
“
0
”
, the timer counts
while the input signal of CNTR
0
pin is at
“
H
”
. If it is
“
1
”
, the timer
counts while the input signal of CNTR
0
pin is at
“
L
”
. When using a
timer in this mode, set the corresponding port P5
2
direction regis-
ter to input mode.
Fig. 19 Structure of timer X mode register
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G
Timer X Write Control
If the timer X write control bit is
“
0
”
, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
If the timer X write control bit is
“
1
”
, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, when the value is written in
latch at the timer underflow, the value is loaded in the timer X and
the latch at the same time. Also, unexpected value may be set in
the high-order counter when the writing in high-order latch and the
underflow of timer X are performed at the same timing.
I
Note on CNTR
0
interrupt active edge selection
CNTR
0
interrupt active edge depends on the CNTR
0
active edge
switch bit.
I
Note on count source selection bit
Except the pulse output mode, write
“
0
”
to the count source selec-
tion bit.
When the timer X count source selection bit is set to
“
1
”
, as for the
recommended operating condition of the main clock input fre-
quency f(X
IN
), the rating value at the high-speed mode is applied.
I
Note on interrupt in pulse output mode
When the count source selection bit is
“
1
”
in the pulse output
mode, the timing when the timer X interrupt request occurs may
be early or lately for one instruction cycle.