SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
10
[CPU Mode Register (CPUM)] 003B
16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B
16
.
After system is released from reset, the ring oscillator mode is se-
lected, and the X
IN
–X
OUT
oscillation and the X
CIN
–X
COUT
oscillation are stopped.
Fig. 7 Structure of CPU mode register
Not available
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Main clock selection bit
0 : X
IN
input signal (X
IN
–
X
OUT
oscillating)
1 : Built-in ring oscillator
(internal system clock: only frequency divided by 8 is valid.)
Port Xc switch bit
0 : I/O port function (Oscillation stop)
1 : X
CIN
–
X
COUT
oscillating function
X
IN
–
X
OUT
oscillation stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
(this bit is invalid when ring oscillator is selected.)
0 : f(X
IN
)/2 (high-speed mode)
1 : f(X
IN
)/8 (middle-speed mode)
Internal system clock selection bit
0 : Main clock selected (middle-/high-speed, ring oscillator mode)
1 : X
CIN
–
X
COUT
selected (low-speed mode)
CPU mode register
(C
P
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M
:
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:
6
8
1
6
)
b
7
b
0
Fig. 8 Switching method of CPU mode register
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Start with a built-in ring oscillator.
Initial value of CPUM is 68
16
.
As for the details of condition for
transition among each mode,
refer to the state transition of system clock.
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.
When the low-, middle- or high-speed mode is used after the X
IN
–
X
OUT
oscillation and the X
CIN
–
X
COUT
oscillation are enabled, wait
in the ring oscillator mode until oscillation stabilizes, and then,
switch the operation mode.
When the middle- and high-speed mode are not used (X
IN
-X
OUT
oscillation and external clock input are not performed), connect
X
IN
to V
CC
through a resistor.