參數(shù)資料
型號： M38B79MFH-XXXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 9/92頁
文件大?。?/td> 4318K
代理商： M38B79MFH-XXXXFP
vi
38B7 Group User’s Manual
List of figures
Fig. 2.4.39 Timing chart (at correct state) of 38B7 Group and M35501FP ...................... 2-127
Fig. 2.4.40 Timing chart (at incorrect state) of 38B7 Group and M35501FP ................... 2-127
Fig. 2.4.41 Setting of relevant registers ................................................................................. 2-128
Fig. 2.4.42 Control procedure ................................................................................................... 2-130
Fig. 2.5.1 Memory assignment of A-D converter relevant registers ................................... 2-133
Fig. 2.5.2 Structure of AD/DA control register ....................................................................... 2-134
Fig. 2.5.3 Structure of A-D conversion register (low-order) ................................................. 2-135
Fig. 2.5.4 Structure of A-D conversion register (high-order) ............................................... 2-135
Fig. 2.5.5 Structure of Interrupt source switch register ........................................................ 2-136
Fig. 2.5.6 Structure of Interrupt request register 2 ............................................................... 2-136
Fig. 2.5.7 Structure of Interrupt control register 2 ................................................................ 2-137
Fig. 2.5.8 Connection diagram ................................................................................................. 2-138
Fig. 2.5.9 Setting of relevant registers ................................................................................... 2-138
Fig. 2.5.10 Control procedure ................................................................................................... 2-139
Fig. 2.6.1 Memory assignment of D-A converter relevant registers ................................... 2-141
Fig. 2.6.2 Structure of D-A conversion register ..................................................................... 2-141
Fig. 2.6.3 Structure of AD/DA control register ....................................................................... 2-142
Fig. 2.6.4 Connection diagram ................................................................................................. 2-143
Fig. 2.6.5 Setting of relevant registers ................................................................................... 2-143
Fig. 2.6.6 Control procedure ..................................................................................................... 2-144
Fig. 2.7.1 Memory assignment of PWM relevant registers .................................................. 2-145
Fig. 2.7.2 Structure of PWM control register ......................................................................... 2-145
Fig. 2.7.3 Structure of PWM register (high-order) ................................................................. 2-146
Fig. 2.7.4 Structure of PWM register (low-order) .................................................................. 2-146
Fig. 2.7.5 Connection diagram ................................................................................................. 2-147
Fig. 2.7.6 Setting of relevant registers ................................................................................... 2-147
Fig. 2.7.7 Control procedure ..................................................................................................... 2-148
Fig. 2.7.8 PWM0 output ............................................................................................................. 2-148
Fig. 2.8.1 Memory assignment of interrupt interval determination function relevant registers
................................................................................................................................... 2-149
Fig. 2.8.2 Structure of Interrupt interval determination register .......................................... 2-149
Fig. 2.8.3 Structure of Interrupt interval determination control register ............................. 2-150
Fig. 2.8.4 Structure of Interrupt edge selection register ...................................................... 2-150
Fig. 2.8.5 Structure of Interrupt request register 1 ............................................................... 2-151
Fig. 2.8.6 Structure of Interrupt control register 1 ................................................................ 2-152
Fig. 2.8.7 Connection diagram ................................................................................................. 2-153
Fig. 2.8.8 Function block diagram ........................................................................................... 2-153
Fig. 2.8.9 Timing chart of data determination ........................................................................ 2-153
Fig. 2.8.10 Setting of relevant registers ................................................................................. 2-154
Fig. 2.8.11 Control procedure ................................................................................................... 2-155
Fig. 2.8.12 Reception of remote-control data (timer 2 interrupt) ........................................ 2-156
Fig. 2.9.1 Memory assignment of watchdog timer relevant register ................................... 2-157
Fig. 2.9.2 Structure of Watchdog timer control register ....................................................... 2-157
Fig. 2.9.3 Structure of CPU mode register ............................................................................ 2-158
Fig. 2.9.4 Connection of watchdog timer and setting of division ratio ............................... 2-159
Fig. 2.9.5 Setting of relevant registers ................................................................................... 2-159
Fig. 2.9.6 Control procedure ..................................................................................................... 2-160
Fig. 2.10.1 Memory assignment of buzzer output circuit relevant register ........................ 2-161
Fig. 2.10.2 Structure of buzzer output control register......................................................... 2-161
Fig. 2.10.3 Connection of buzzer output circuit and setting of division ratio.................... 2-162
Fig. 2.10.4 Setting of relevant register ................................................................................... 2-162
Fig. 2.10.5 Control procedure ................................................................................................... 2-162
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