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參數(shù)資料
| 型號： | M38B79MFH-XXXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 39/92頁 |
| 文件大?。?/td> | 4318K |
| 代理商： | M38B79MFH-XXXXFP |
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HARDWARE
38B7 Group User’s Manual
1-21
INTERRUPTS
Interrupts occur by twenty two sources: five external, sixteen inter-
nal, and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an inter-
rupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are “1” and the interrupt disable flag is
“0.” Interrupt enable bits can be set or cleared by software. Interrupt
request bits can be cleared by software, but cannot be set by soft-
ware. The BRK instruction interrupt and reset cannot be disabled
with any flag or bit. The I flag disables all interrupts except the BRK
instruction interrupt and reset. If several interrupts requests occur at
the same time, the interrupt with highest priority is accepted first.
Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Source Selection
Any of the following interrupt sources can be selected by the inter-
rupt source switch register (address 003916).
1. INT1 or Serial I/O3
2. INT3 or Serial I/O2 transmit
3. INT4 or A-D conversion
sNote
When setting the followings, the interrupt request bit may be set to
“1”.
When switching external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
When switching interrupt sources of an interrupt vector address where
two or more interrupt sources are allocated
Related register: Interrupt source switch register (address 3916)
When not requiring the interrupt occurrence synchronized with these
setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge select bit (active edge switch bit) or the
interrupt (source) select/switch bit.
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
FUNCTIONAL DESCRIPTION
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