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| 型號： | M38B79MFH-XXXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 11/92頁 |
| 文件大小： | 4318K |
| 代理商： | M38B79MFH-XXXXFP |
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viii
38B7 Group User’s Manual
List of figures
Fig. 3.4.1 Wiring for the RESET pin ......................................................................................... 3-28
Fig. 3.4.2 Wiring for clock I/O pins ........................................................................................... 3-29
Fig. 3.4.3 Wiring for CNVss pin ................................................................................................. 3-29
Fig. 3.4.4 Wiring for the VPP pin of the flash memory version .............................................. 3-30
Fig. 3.4.5 Bypass capacitor across the VSS line and the VCC line ........................................ 3-30
Fig. 3.4.6 Analog signal line and a resistor and a capacitor ................................................ 3-31
Fig. 3.4.7 Wiring for a large current signal line ...................................................................... 3-32
Fig. 3.4.8 Wiring of signal lines where potential levels change frequently ......................... 3-32
Fig. 3.4.9 VSS pattern on the underside of an oscillator ........................................................ 3-33
Fig. 3.4.10 Setup for I/O ports ................................................................................................... 3-33
Fig. 3.4.11 Watchdog timer by software ................................................................................... 3-34
Fig. 3.5.1 Structure of Port Pi (i =0–7, 9, A)........................................................................... 3-35
Fig. 3.5.2 Structure of Port P8................................................................................................... 3-35
Fig. 3.5.3 Structure of Port PB .................................................................................................. 3-36
Fig. 3.5.4 Structure of Port Pi direction register (i = 1, 3–7, 9, A) ...................................... 3-36
Fig. 3.5.5 Structure of Port P8 direction register .................................................................... 3-37
Fig. 3.5.6 Structure of Port PB direction register .................................................................... 3-37
Fig. 3.5.7 Structure of Serial I/O1 automatic transfer data pointer ...................................... 3-38
Fig. 3.5.8 Structure of Serial I/O1 control register 1 .............................................................. 3-38
Fig. 3.5.9 Structure of Serial I/O1 control register 2 .............................................................. 3-39
Fig. 3.5.10 Structure of Serial I/O1 register/Transfer counter ............................................... 3-40
Fig. 3.5.11 Structure of Serial I/O1 control register 3 ............................................................ 3-41
Fig. 3.5.12 Structure of Serial I/O2 control register ................................................................ 3-42
Fig. 3.5.13 Structure of Serial I/O2 status register ................................................................. 3-43
Fig. 3.5.14 Structure of Serial I/O2 transmit/receive buffer register ..................................... 3-43
Fig. 3.5.15 Structure of Timer i ................................................................................................. 3-44
Fig. 3.5.16 Structure of Timer 2 ................................................................................................3-44
Fig. 3.5.17 Structure of PWM control register ......................................................................... 3-44
Fig. 3.5.18 Structure of Timer 6 PWM register ....................................................................... 3-45
Fig. 3.5.19 Structure of Timer 12 mode register ..................................................................... 3-45
Fig. 3.5.20 Structure of Timer 34 mode register ..................................................................... 3-46
Fig. 3.5.21 Structure of Timer 56 mode register ..................................................................... 3-46
Fig. 3.5.22 Structure of D-A conversion register ..................................................................... 3-47
Fig. 3.5.23 Structure of Timer X (low-order, high-order) ........................................................ 3-47
Fig. 3.5.24 Structure of Timer X mode register 1 ................................................................... 3-48
Fig. 3.5.25 Structure of Timer X mode register 2 ................................................................... 3-49
Fig. 3.5.26 Structure of Interrupt interval determination register .......................................... 3-49
Fig. 3.5.27 Structure of Interrupt interval determination control register ............................. 3-50
Fig. 3.5.28 Structure of AD/DA control register ....................................................................... 3-51
Fig. 3.5.29 Structure of A-D conversion register (low-order) ................................................. 3-51
Fig. 3.5.30 Structure of A-D conversion register (high-order) ............................................... 3-52
Fig. 3.5.31 Structure of PWM register (high-order)................................................................. 3-52
Fig. 3.5.32 Structure of PWM register (low-order) .................................................................. 3-53
Fig. 3.5.33 Structure of Baud rate generator ........................................................................... 3-53
Fig. 3.5.34 Structure of UART control register ........................................................................ 3-54
Fig. 3.5.35 Structure of Interrupt source switch register ........................................................ 3-55
Fig. 3.5.36 Structure of Interrupt edge selection register ...................................................... 3-56
Fig. 3.5.37 Structure of CPU mode register ............................................................................ 3-57
Fig. 3.5.38 Structure of Interrupt request register 1 ............................................................... 3-58
Fig. 3.5.39 Structure of Interrupt request register 2 ............................................................... 3-59
Fig. 3.5.40 Structure of Interrupt control register 1 ................................................................ 3-60
Fig. 3.5.41 Structure of Interrupt control register 2 ................................................................ 3-61
Fig. 3.5.42 Structure of Serial I/O3 control register ................................................................ 3-62
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