參數(shù)資料
型號(hào)： M38B79MFH-XXXXFP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù)： 10/92頁(yè)
文件大?。?/td> 4318K
代理商： M38B79MFH-XXXXFP
vii
38B7 Group User’s Manual
List of figures
Fig. 2.11.1 Example of power-on reset circuit ....................................................................... 2-163
Fig. 2.11.2 RAM backup system example .............................................................................. 2-163
Fig. 2.12.1 Structure of CPU mode register .......................................................................... 2-165
Fig. 2.12.2 Connection diagram ............................................................................................... 2-166
Fig. 2.12.3 Status transition diagram during power failure .................................................. 2-166
Fig. 2.12.4 Setting of relevant registers ................................................................................. 2-167
Fig. 2.12.5 Control procedure ................................................................................................... 2-168
Fig. 2.12.6 Structure of clock counter ..................................................................................... 2-169
Fig. 2.12.7 Initial setting of relevant registers ....................................................................... 2-170
Fig. 2.12.8 Setting of relevant registers after detecting power failure ............................... 2-171
Fig. 2.12.9 Control procedure ................................................................................................... 2-172
Fig. 2.13.1 Memory map of flash memory version for 38B7 Group ................................... 2-174
Fig. 2.13.2 Memory map of registers relevant to flash memory ......................................... 2-175
Fig. 2.13.3 Structure of Flash memory control register ........................................................ 2-175
Fig. 2.13.4 Structure of Flash command register .................................................................. 2-176
Fig. 2.13.5 Structure of CPU mode register .......................................................................... 2-176
Fig. 2.13.6 Reprogramming example of built-in flash memory by serial I/O mode .......... 2-179
Fig. 2.13.7 Processing example of pins on board in serial I/O mode (1) ......................... 2-180
Fig. 2.13.8 Processing example of pins on board in serial I/O mode (2) ......................... 2-180
Fig. 2.13.9 Processing example of pins on board in serial I/O mode (3) ......................... 2-181
Fig. 2.13.10 Example for reprogramming system of built-in flash memory by CPU reprogramming
mode ....................................................................................................................... 2-182
Fig. 2.13.11 CPU reprogramming control program example (1) ......................................... 2-183
Fig. 2.13.12 CPU reprogramming control program example (2) ......................................... 2-184
Fig. 2.13.13 CPU reprogramming control program example (3) ......................................... 2-185
Fig. 2.13.14 CPU reprogramming control program example (4) ......................................... 2-186
Fig. 2.13.15 VPP control circuit example (1) ........................................................................... 2-187
Fig. 2.13.16 VPP control circuit example (2) ........................................................................... 2-187
CHAPTER 3 APPENDIX
Fig. 3.1.1 Circuit for measuring output switching characteristics ............................................ 3-8
Fig. 3.1.2 Timing diagram ............................................................................................................. 3-9
Fig. 3.2.1 Power source current standard characteristics ...................................................... 3-10
Fig. 3.2.2 Power source current standard characteristics (in wait mode) ........................... 3-10
Fig. 3.2.3 High-breakdown P-channel open-drain output port characteristics (25
°C) ....... 3-11
Fig. 3.2.4 High-breakdown P-channel open-drain output port characteristics (90
°C) ....... 3-11
Fig. 3.2.5 CMOS output port P-channel side characteristics (25
°C) .................................. 3-12
Fig. 3.2.6 CMOS output port P-channel side characteristics (90
°C) .................................. 3-12
Fig. 3.2.7 CMOS output port N-channel side characteristics (25
°C) .................................. 3-13
Fig. 3.2.8 CMOS output port N-channel side characteristics (90
°C) .................................. 3-13
Fig. 3.2.9 A-D conversion standard characteristics ................................................................. 3-14
Fig. 3.3.1 Setting procedure of relevant registers ................................................................... 3-15
Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-16
Fig. 3.3.3 Structure of interrupt control register 2 .................................................................. 3-16
Fig. 3.3.4 Sequence of setting serial I/O2 control register again ......................................... 3-20
Fig. 3.3.5 PWM0 output ............................................................................................................... 3-22
Fig. 3.3.6 Initialization of processor status register ................................................................ 3-24
Fig. 3.3.7 Sequence of PLP instruction execution .................................................................. 3-24
Fig. 3.3.8 Stack memory contents after PHP instruction execution ..................................... 3-24
Fig. 3.3.9 Status flag at decimal calculations .......................................................................... 3-25
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