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參數(shù)資料
| 型號： | M38B79MFH-A055FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 91/109頁 |
| 文件大小： | 1559K |
| 代理商： | M38B79MFH-A055FP |
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91
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
G
Erase command
Input command code 20
16
in the first transfer and command code
20
16
again in the second transfer. When this is done, the
M38B79FF executes an erase command. Erase is initiated at the
last rising edge of the serial clock. The BUSY pin is driven high
during the erase operation. Erase is completed within 9.5 ms as
measured by the internal timer, and the BUSY pin is pulled low.
Note that data 00
16
must be written to all memory locations before
executing the erase command.
Note:
A erase operation is not completed by executing the erase
command once. Always be sure to execute a erase verify
command after executing the erase command. When the fail-
ure is found in the verification, the user must repeatedly ex-
ecute the erase command until the pass in the verification.
Refer to Figure 90 for the erase flowchart.
Fig. 95 Timings at erasing
G
Erase verify command
The user must verify the contents of all addresses after complet-
ing the erase command. Input command code A0
16
in the first
transfer. Proceed and input the low-order 8 bits and the high-order
8 bits of the address and pull the OE pin low. When this is done,
the M38B79FF reads out the contents of the specified address,
and then latchs it into the internal data latch. When the OE pin is
released back high and serial clock is input to the SCLK pin, the
verify data that has been latched into the data latch is serially out-
put from the SDA pin.
Note:
If any memory location where the contents have not been
erased is found in the erase verify operation, execute the op-
eration of
“
erase
→
erase verify
”
over again. In this case,
however, the user does not need to write data 00
16
to memory
locations before erasing.
Fig. 96 Timings during erase verify
tw
E
SCLK
BUSY
OE
SDA
t
CH
t
EC
0 0 0 0 0 1 0 0
Command code input (20
16
) Command code input (20
16
)
0 0 0 0 0 1 0 0
Erase
“
H
”
“
L
”
SCLK
BUSY
OE
SDA
t
CH
A
0
A
7
A
8
A
15
D
0
D
7
t
CH
t
CREV
Command code input (A0
16
) Verify address input (L)
Verify address input (H)
Verify data output
t
WR
Verify read
t
RC
Note :
When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th
(C-E)
after the last rising edge of SCLK (at the 8th bit).
0 0 0 0 0 1 0 1
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