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參數(shù)資料
| 型號： | M38B79MFH-A055FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 63/109頁 |
| 文件大小： | 1559K |
| 代理商： | M38B79MFH-A055FP |
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
63
1
5
P
S
S
.
7
5
μ
s
6
4
μ
s
6
4
μ
s
6
4
μ
s
6
4
μ
s
6
4
μ
s
m
=
0
m
=
7
m
=
8
m
=
9
m
=
6
3
1
6
.
0
μ
s
1
5
.
7
5
μ
s
1
5
.
7
5
μ
s
1
5
.
7
5
μ
s
1
5
.
7
5
μ
s
1
5
.
7
5
μ
s
u
l
l
b
b
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-
p
-
p
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“
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o
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:
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0
0
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1
0
1
1
1
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6
5
1
0
.
.
1
1
0
7
1
1
u
u
u
:
r
r
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s
5
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s
:
m
:
=
=
8
,
a
2
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4
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,
t
3
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2
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r
4
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0
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,
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5
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6
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m
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4
0
9
6
μ
s
Data Setup
The PWM output pin also function as port P9
6
. Set port P9
6
to be
the PWM output pin by setting bit 0 of the PWM control register
(address 0026
16
) to
“
1
”
. The high-order 8 bits of output data are
set in the high-order PWM register PWMH (address 0035
16
) and
the low-order 6 bits are set in the low-order PWM register PWML
(address 0036
16
).
PWM Operation
The timing of the 14-bit PWM function is shown in Figure 65.
The 14-bit PWM data is divided into the low-order 6 bits and the
high-order 8 bits in the PWM latch.
The high-order 8 bits of data determine how long an
“
H
”
level sig-
nal is output during each sub-period. There are 64 sub-periods in
each period, and each sub-period t is 256
τ
(= 64
μ
s) long. The
signal
’
s
“
H
”
has a length equal to N times
τ
, and its minimum reso-
lution = 250 ns.
The last bit of the sub-period becomes the ADD bit which is speci-
fied either
“
H
”
or
“
L,
”
by the contents of PWML. As shown in Table
11, the ADD bit is decided either
“
H
”
or
“
L.
”
That is, only in the sub-period tm shown in Table 11 in the PWM
cycle period T = 64 t, the
“
H
”
duration is lengthened during the
minimum resolution width
τ
period in comparison with the other
period.
For example, if the high-order eight bits of the 14-bit data are
“
03
16
”
and the low-order six bits are
“
05
16
,
”
the length of the
“
H
”
level output in sub-periods t8, t24, t32, t40 and t56 is 4
τ
, and its
length 3
τ
in all other sub-periods.
Time at the
“
H
”
level of each sub-period almost becomes equal
because the time becomes length set in the high-order 8 bits or
becomes the value plus t, and this sub-period t (= 64
μ
s, approxi-
mate 15.6 kHz) becomes cycle period approximately.
Table 11 Relationship between low-order 6-bit data and setting
period of ADD bit
Low-order
6-bit data
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 1 0 0
0 0 1 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0
None
m = 32
m = 16, 48
m = 8, 24, 40, 56
m = 4, 12, 20, 28, 36, 44, 52, 60
m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63
LSB
Sub-periods tm lengthened (m = 0 to 63)
Transfer From Register to Latch
Data written to the PWML register is transferred to the PWM latch
once in each PWM period (every 4096
μ
s), and data written to the
PWMH register is transferred to the PWM latch once in each sub-
period (every 64
μ
s). Pulses output from the PWM output pin
correspond to this latch contents.
When the PWML register is read, the contents of the latch are
read. However, bit 7 of the PWML register indicates whether the
transfer to the PWM latch is completed: the transfer is completed
when bit 7 is
“
0
”
, it is not done when bit 7 is
“
1
”
.
Fig. 65 PWM timing
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