參數(shù)資料
型號(hào)： M38B79MFH-A055FP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 31/109頁(yè)
文件大?。?/td> 1559K
代理商： M38B79MFH-A055FP
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
31
(2) 8-bit serial I/O mode
Address 001B
16
is assigned to the serial I/O1 register.
When the internal synchronous clock is selected, a serial transfer
of the 8-bit serial I/O is started by a write signal to the serial I/O1
register (address 001B
16
).
The serial transfer status flag (b5 of address 001A
16
) of serial I/O1
control register 2 indicates the shift register status of serial I/O1,
and is set to “1” by writing into the serial I/O1 register, which be-
comes a transfer start trigger and reset to “0” after completion of
8-bit transfer. At the same time, a serial I/O1 interrupt request oc-
curs.
When the external synchronous clock is selected, the contents of
the serial I/O1 register are continuously shifted while transfer
clocks are input to S
CLK1
. Therefore, the clock needs to be con-
trolled externally.
(3) Automatic transfer serial I/O mode
The serial I/O1 automatic transfer controller controls the write and
read operations of the serial I/O1 register, so that the function of
address 001B
16
is used as a transfer counter (1-byte unit).
When performing serial transfer through the serial I/O automatic
transfer RAM (addresses 0F00
16
to 0FFF
16
), it is necessary to set
the serial I/O1 automatic transfer data pointer (address 0018
16
)
beforehand.
Input the low-order 8 bits of the first data store address to be seri-
ally transferred to the automatic transfer data pointer set bits.
When the internal synchronous clock is selected, the transfer in-
terval for each 1-byte data can be set by the automatic transfer
interval set bits (b0 to b4 of address 001C
16
) of serial I/O1 control
register 3 in the following cases:
1. When using no handshake signal
2. When using the S
RDY1
output, S
BUSY1
output, and S
STB1
output
of the handshake signal independently
3. When using a combination of S
RDY1
output and S
STB1
output or
a combination of S
BUSY1
output and S
STB1
output of the hand-
shake signal.
It is possible to select one of 32 different values, namely 2 to 33
cycles of the transfer clock, as a setting value.
When using the S
BUSY1
output and selecting the S
BUSY1
output
S
STB1
output function selection bit (b4 of address 001A
16
) of serial
I/O1 control register 2 as the signal for all transfer data, provided
that the automatic transfer interval setting is valid, a transfer inter-
val is placed before the start of transmission/reception of the first
data and after the end of transmission/reception of the last data.
For S
STB1
output, regardless of the contents of the S
BUSY1
output
S
STB1
output function selection bit (b4), the transfer interval for
each 1-byte data is longer than the set value by 2 cycles.
Furthermore, when using a combination of S
BUSY1
output and
S
STB1
output as a signal for all transfer data, the transfer interval
after the end of transmission/reception of the last data is longer
than the set value by 2 cycles.
When the external synchronous clock is selected, automatic trans-
fer interval setting is disabled.
After completion of the above bit setup, if the internal synchronous
clock is selected, automatic serial transfer is started by writing the
value of “number of transfer bytes – 1” into the transfer counter
(address 001B
16
).
When the external synchronous clock is selected, write the value
of “number of transfer bytes – 1” into the transfer counter and
keep an internal system clock interval of 5 cycles or more. After
that, input transfer clock to S
CLK1
.
As a transfer interval for each 1-byte data transfer, keep an inter-
nal system clock interval of 5 cycles or more from the clock rise
time of the last bit.
Regardless of whether the internal or external synchronous clock
is selected, the automatic transfer data pointer and the transfer
counter are decremented after each 1-byte data is received and
then written into the automatic transfer RAM. The serial transfer
status flag (b5 of address 001A
16
) is set to “1” by writing data into
the transfer counter. Writing data becomes a transfer start trigger,
and the serial transfer status flag is reset to “0” after the last data
is written into the automatic transfer RAM. At the same time, a se-
rial I/O1 interrupt request occurs.
The values written in the automatic transfer data pointer set bits
(b0 to b7 of address 0018
16
) and the automatic transfer interval
set bits (b0 to b4 of address 001C
16
) are held in the latch.
When data is written into the transfer counter, the values latched
in the automatic transfer data pointer set bits (b0 to b7) and the
automatic transfer interval set bits (b0 to b4) are transferred to the
decrement counter.
Fig. 24 Structure of serial I/O1 automatic transfer data pointer
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