
ix
38B7 Group User’s Manual
List of figures
Fig. 3.5.43 Structure of Serial I/O3 register ............................................................................. 3-62
Fig. 3.5.44 Structure of Watchdog timer control register ....................................................... 3-63
Fig. 3.5.45 Structure of Pull-up control register 3 ................................................................... 3-63
Fig. 3.5.46 Structure of Pull-up control register 1 ................................................................... 3-64
Fig. 3.5.47 Structure of Pull-up control register 2 ................................................................... 3-64
Fig. 3.5.48 Structure of Port P0 digit output set switch register .......................................... 3-65
Fig. 3.5.49 Structure of Port P2 digit output set switch register .......................................... 3-65
Fig. 3.5.50 Structure of FLDC mode register .......................................................................... 3-66
Fig. 3.5.51 Structure of Tdisp time set register ...................................................................... 3-67
Fig. 3.5.52 Structure of Toff1 time set register ....................................................................... 3-68
Fig. 3.5.53 Structure of Toff2 time set register ....................................................................... 3-68
Fig. 3.5.54 Structure of FLD data pointer/FLD data pointer reload register ....................... 3-69
Fig. 3.5.55 Structure of Port P4FLD/port switch register ....................................................... 3-69
Fig. 3.5.56 Structure of Port P5FLD/port switch register ....................................................... 3-70
Fig. 3.5.57 Structure of Port P6FLD/port switch register ....................................................... 3-70
Fig. 3.5.58 Structure of FLD output control register ............................................................... 3-71
Fig. 3.5.59 Structure of Buzzer output control register .......................................................... 3-72
Fig. 3.5.60 Structure of Flash memory control register .......................................................... 3-73
Fig. 3.5.61 Structure of Flash command register .................................................................... 3-74
Fig. 3.9.1 Pin configuration of M35501FP ................................................................................ 3-88
Fig. 3.9.2 Functional block diagram .......................................................................................... 3-89
Fig. 3.9.3 Port block diagram ..................................................................................................... 3-90
Fig. 3.9.4 Digit setting ................................................................................................................. 3-91
Fig. 3.9.5 16-digit mode output waveform ................................................................................ 3-92
Fig. 3.9.6 Optional digit mode output waveform...................................................................... 3-92
Fig. 3.9.7 Cascade mode connection example: 17 digits or more selected ....................... 3-93
Fig. 3.9.8 Cascade mode output waveform .............................................................................. 3-93
Fig. 3.9.9 Connection example with 38B7 Group microcomputer (1 to 16 digits) ............. 3-94
Fig. 3.9.10 Connection example with 38B7 Group microccomputer (17 to 32 digits) ....... 3-94
Fig. 3.9.11 Digit output waveform when reset signal is input ............................................... 3-95
Fig. 3.9.12 Power-on reset circuit .............................................................................................. 3-96
Fig. 3.9.13 Timing diagram ......................................................................................................... 3-99