參數(shù)資料
型號: M38B79FFFP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 57/109頁
文件大?。?/td> 1559K
代理商: M38B79FFFP
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
57
P6
4
to P6
7
Expansion Function
Ports P6
4
to P6
7
are CMOS output structure. FLD digit outputs
can be increased as many as 16 lines by connecting a decoder
converting 4-bit to 16-bit data to these ports. P6
4
to P6
7
have the
function to allow for connection to a decoder converting 4-bit to
16-bit data.
(1) P6
4
to P6
7
Toff invalid function
This function disables the Toff1 time and Toff2 time and outputs
display data for the duration of Tdisp. (See Figure 57.) This can be
achieved by setting the P6
4
to P6
7
Toff invalid bit (bit 2 of address
0EFC
16
) to
1
.
(2) Dimmer signal output function
This function allows a dimmer signal creation signal to be output
from DIM
OUT
(P7
3
). The dimmer function can be achieved by con-
trolling the decoder with this signal. (See Figure 57.) This function
can be set by setting P7
3
dimmer output control bit (bit 4 of ad-
dress 0EFC
16
) to
1
.
Unlike the Toff section generating/nothing function, this function
disables all display data.
Fig. 57 P6
4
to P6
7
FLD output pulses
(3) P6
4
to P6
7
FLD output reverse function
P6
4
to P6
7
have the function to reverse the polarity of the FLD out-
put. This function is useful in adjusting the polarity when using an
externally installed driver.
The output polarity can be reversed by setting the P6
4
to P6
7
out-
put reverse bit of the FLD output control register (bit 0 of address
0EFC
16
) to
1
.
I
Note
In the case of gradation display mode and dark display, P6
4
to P6
7
Toff invalid function is disabled.
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