參數(shù)資料
型號： M38B79FFFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 15/109頁
文件大?。?/td> 1559K
代理商： M38B79FFFP
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
15
Table 6 List of I/O port functions (1)
Pin
P0
0
/FLD
8
–
P0
7
/FLD
15
Nama
Port P0
Input/Output
Output
I/O Format
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output
Low-voltage input level
(port input)
CMOS compatible input
level (RxD, S
CLK21
,
S
CLK22
)
CMOS 3-state output
Non-Port Function
FLD automatic display
function
Related SFRs
FLDC mode register
P0 digit output set switch
register
Ref.No.
(1)
(2)
FLDC mode register
FLD automatic display
function
Serial I/O2 function I/O
P1
0/
FLD
16
–
P1
7
/FLD
23
Port P1
Input/output,
individual
bits
FLDC mode register
P2 digit output set switch
register
(1)
P2
0
/FLD
0
–
P2
7
/FLD
7
Port P2
Output
P3
0
/FLD
24
–
P3
7
/FLD
31
Port P3
Input/output,
individual
bits
FLDC mode register
(2)
FLDC mode register
Port P4 FLD/Port switch
register
(2)
P4
0
/FLD
32
–
P4
7
/FLD
39
Port P4
Input/output,
individual
bits
Input/output,
individual
bits
P5
0
/FLD
40
–
P5
7
/FLD
47
Port P5
FLDC mode register
Port P5 FLD/Port switch
register
(2)
FLDC mode register
Port P6 FLD/Port switch
register
(2)
Input/output,
individual
bits
Port P6
P6
0
/FLD
48
–
P6
3
/FLD
51
P6
4
/RxD/
FLD
52
P6
5
/TxD/
FLD
53
,
P6
6
/S
CLK21
/
FLD
54
P6
7
/S
RDY2
/
S
CLK22
/
FLD
55
P7
0
/INT
0
,
P7
1
/INT
1
P7
2
/INT
2
CMOS compatible input
level
CMOS 3-state output
FLDC mode register
Serial I/O2 control
register
UART control register
Interrupt edge selection
register
(3)
(4)
(5)
(6)
Port P7
Input/output,
individual
bits
External interrput input
Interrupt edge selection
register
Interrupt interval determi-
nation control register
Interrupt edge selection
register
FLD output control register
Timer 56 mode register
Timer 12 mode register
Timer 34 mode register
Buzzer output control
register
Interrupt edge selection
register
CPU mode register
(7)
P7
3
/INT
3
/
DIM
OUT
External interrput input
Dimmer signal output
(8)
P7
4
/PWM
1
P7
5
/T1
OUT
P7
6
/T3
OUT
P7
7
/INT
4
/
B
UZ01
CMOS compatible input
level
CMOS 3-state output
PWM output
Timer output
Timer output
Buzzer output
External interrput input
(9)
Sub-clock generating
circuit I/O
External count input
P8
0
/X
CIN
P8
1
/X
COUT
P8
2
/CNTR
1
P8
3
/CNTR
0
/
CNTR
2
Port P8
Input/output,
individual
bits
(10)
(11)
(6)
(12)
Interrupt edge selection
register
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