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參數(shù)資料
| 型號： | M38B79FFFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 4/109頁 |
| 文件大?。?/td> | 1559K |
| 代理商： | M38B79FFFP |
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
4
Table 1 Pin description (1)
Pin
Name
Function
V
CC
, V
SS
CNV
SS
Power source
CNV
SS
Apply voltage of 4.0
–
5.5 V to V
CC
,
and 0 V to V
SS
.
Connect to V
SS
.
VPP power input pin in flash memory mode.
Apply voltage supplied to pull-down resistors of ports P0, P1, P2 and P3.
V
EE
Pull-down
power source
Reference voltage
Analog power
source
Reset input
Clock input
V
REF
AV
SS
Reference voltage input pin for A-D converter.
Analog power source input pin for A-D converter.
Connect to V
SS
.
Reset input pin for active
“
L
”
.
Input and output pins for the main clock generating circuit.
Feedback resistor is built in between X
IN
pin and X
OUT
pin.
Connect a ceramic resonator or quartz-crystal oscillator between the X
IN
and X
OUT
pins to set the
oscillation frequency.
When an external clock is used, connect the clock source to the X
IN
pin and leave the X
OUT
pin open.
The clock is used as the oscillating source of system clock.
8-bit output port.
High-breakdown-voltage P-channel open-drain output structure.
A pull-down resistor is built in between port P0 and the V
EE
pin.
At reset, this port is set to V
EE
level.
8-bit I/O port.
I/O direction register allows each pin to be individually programmed as either pins
input or output.
At reset, this port is set to input mode.
Low-voltage input level.
High-breakdown-voltage P-channel open-drain output structure.
A pull-down resistor is built in between port P1 and the V
EE
pin.
At reset, this port is set to V
EE
level.
8-bit output port with the same function as port P0.
High-breakdown-voltage P-channel open-drain output structure.
A pull-down resistor is built in between port P2 and the V
EE
pin.
At reset, this port is set to V
EE
level.
8-bit I/O port with the same function as port P1.
Low-voltage input level.
High-breakdown-voltage P-channel open-drain output structure.
A pull-down resistor is built in between port P3 and the V
EE
pin.
At reset, this port is set to V
EE
level.
8-bit I/O port with the same function as port P1.
Low-voltage input level.
High-breakdown-voltage P-channel open-drain output structure.
A pull-down resistor is not built in between port P4 and the V
EE
pin.
8-bit I/O port with the same function as port P1.
Low-voltage input level.
High-breakdown-voltage P-channel open-drain output structure.
A pull-down resistor is not built in between port P5 and the V
EE
pin.
4-bit I/O port with the same function as port P1.
Low-voltage input level.
High-breakdown-voltage P-channel open-drain output structure.
A pull-down resistor is not built in between port P6 and the V
EE
pin.
______
RESET
X
IN
X
OUT
Clock output
P0
0
/FLD
8
–
P0
7
/FLD
15
Output port P0
FLD automatic display
pins
P1
0
/FLD
16
–
I/O port P1
P1
7
/FLD
23
FLD automatic display
P2
0
/FLD
0
–
P2
7
/FLD
7
Output port P2
FLD automatic display
pins
P3
0
/FLD
24
–
I/O port P3
P3
7
/FLD
31
FLD automatic display
pins
P4
0
/FLD
32
–
I/O port P4
P4
7
/FLD
39
FLD automatic display
pins
P5
0
/FLD
40
–
I/O port P5
P5
7
/FLD
47
FLD automatic display
pins
P6
0
/FLD
48
–
I/O port P6
P6
3
/FLD
51
FLD automatic display
pins
Function except a port function
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