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3874 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Fig. 70 Ceramic resonator circuit
Fig. 71 External clock input circuit
XCIN
XCOUT
XIN
XOUT
Open
External oscillation
circuit
VCC
VSS
CCIN
CCOUT
Rf
Rd
CLOCK GENERATING CIRCUIT
The 3874 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
(1) Middle-speed mode
The internal clock
φ is the frequency of XIN divided by 8. After re-
set, this mode is selected.
(2) Double-speed mode
The internal clock
φ is the frequency of XIN.
(3) High-speed mode
The internal clock
φ is half the frequency of XIN.
(4) Low-speed mode
The internal clock
φ is half the frequency of XCIN.
s Note
When switching the mode between double/middle/high-speed and
low-speed, stabilize both XIN and XCIN oscillations. Sufficient time
is required for the sub clock to stabilize, especially immediately af-
ter power on and at returning from stop mode. When switching the
mode between double/middle/high-speed and low-speed, set the
frequency on condition that f(XIN) > 3f(XCIN).
It takes the cycle number mentioned below to switch between
each mode (machine cycle = cycle of internal clock
φ).
Double-speed mode
→Except double-speed mode
1 to 8 machine cycles
High-speed mode
→Except high-speed mode
1 to 4 machine cycles
Middle-speed mode
→Except middle-speed mode
1 machine cycle
Low-speed mode
→Except low-speed mode
1 to 4 machine cycles
The 3874 group operates in the previous mode while the mode is
switched.
(5) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1”. When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
By clearing furthermore the XCOUT drivability selection bit (b3) of
the CPU mode register to “0”, low power consumption operation
can be realized by reducing the drivability between XCIN and
XCOUT. At reset or during STP instruction execution this bit is set
to “1” and a reduced drivability that has an easy oscillation start is
set. The sub-clock XCIN-XCOUT oscillating circuit can no directly in-
put clocks that are generated externally. Accordingly, make sure to
cause an external resonator to oscillate.
Oscillation Control
(1) Stop mode
When the STP instruction is executed, the internal clock
φ stops at
an “H” level, and XIN and XCIN oscillators stop. The value set to the
timer 1 latch and the timer 2 latch is set to timer 1 and timer 2. Ei-
ther XIN or XCIN divided by 16 is input to timer 1 as count source,
and the output of timer 1 is connected to timer 2. The bits of the
timer 123 mode register except the timer 3 count source selection
bit (b4) are cleared to “0”. Set the interrupt enable bits of timer 1
and timer 2 to the disabled state (“0”) before executing the STP in-
struction.
Oscillator restarts at reset or when an external interrupt is re-
ceived, but the internal clock
φ is not supplied to the CPU until
timer 2 underflows. This allows time for the clock circuit oscillation
to stabilize. Timer 1 latch and timer 2 latch should be set to proper
values for stabilizing oscillation before executing the STP instruc-
tion.
(2) Wait mode
If the WIT instruction is executed, the internal clock
φ stops at an
“H” level. The states of XIN and XCIN are the same as the state be-
fore executing the WIT instruction. The internal clock
φ restarts at
reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
clock is restarted.
XCIN
XCOUT
XIN
XOUT
CIN
COUT
CCIN
CCOUT
Rf
Rd