3874 Group User’s Manual
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APPENDIX
3.3 Notes on use
3.3.6 Notes on serial I/O2
(1)
When using external clock
q The serial I/O2 interrupt request bit is set to “1” by counting eight times of the transfer clock when
the synchronous clock is the internal clock or the external clock. However, when using the external
clock, the contents of the serial I/O2 register is being shifted continuously while the transfer clock
is input to the serial I/O2’s circuit. Stop the transfer clock at 8 times. (When using the internal
clock, the transfer clock automatically stops.)
q When using the external clock, the SOUT2 pin does not become the high-impedance state after the
data transfer is completed. Set “1” to the SOUT2 output control bit of the serial I/O2 control register
after the data transfer is completed.
When using the internal clock, the SOUT2 pin automatically becomes the high-impedance state after
the data transfer is completed.
q When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the SCLK2 input level. Also, write data to the serial I/O2 register at “H”
of the SCLK2 input level.
3.3.7 Notes on serial I/O3
(1)
In all modes
s State of SOUT3 pin
q The SOUT3 output control bit of the serial I/O3 control register 2 can be used to select the state
of the SOUT3 pin when serial data is not transferred; either output active or high-impedance.
However, when selecting an external synchronous clock; the SOUT3 pin can become the high-
impedance state by setting the SOUT3 output control bit to “1” when SCLK3 input is at “H” after
transfer completion.
s Serial I/O initialization bit
q Set “0” to the serial I/O initialization bit of the serial I/O3 control register 1 when terminating a
serial transfer during transferring.
q When writing “1” to the serial I/O initialization bit, serial I/O3 is enabled, but each register is not
initialized. Set the value of each register by program.
s Handshake signal
q SBUSY3 input signal
Input an “H” level to the SBUSY3 input and an “L” level signal to the SBUSY3 input in the initial state.
When the external synchronous clock is selected, switch the input level to the SBUSY3 input and
the SBUSY3 input while the SCLK3 input is in “H” state.
q SRDY3 inputoutput signal
When selecting the internal synchronous clock, input an “L” level to the SRDY3 input and an “H”
level signal to the SRDY3 input in the initial state.
(2)
8-bit serial I/O mode
s When selecting external synchronous clock
When an external synchronous clock is selected, the contents of the serial I/O3 register are being
shifted continually while the transfer clock is input to SCLK3. In this case, control the clock externally.