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參數(shù)資料
| 型號(hào)： | M38747MCF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 6.4 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 14 MM, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 176/358頁(yè) |
| 文件大?。?/td> | 4216K |
| 代理商： | M38747MCF |
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2-166
3874 Group User's Manual
APPLICATION
2.9 Clock generating circuit
2.9.4 Notes on use
(1)
In all mode
q Use the circuit constants recommended by the resonator manufacturer.
q No external resistor is needed between pins XIN and XOUT because a feed-back resistor is included.
However, an external feed-back resistor is needed between pins XCIN and XCOUT.
q Use the oscillation circuit of the XCIN side in the condition that the pull-up circuit between pins XCIN
and XCOUT is valid.
q If switching the mode between low-speed
and double-speed, switch the mode to
middle/high-speed first, and then switch the
mode to double-speed by program. Do not
switch the mode from low-speed to double-
speed directly. 1 to 4 machine cycles are
required for switching from low-speed mode
to other mode. Insert “clock switch timing
wait” for switching the mode to middle/high-
speed certainly, and then switch the mode
to double-speed.
Table 2.9.1 lists the recommended transition
process for system clock switch.
Figure 2.9.12 shows the program example.
q When switching between the modes, set
the frequency under the condition of f(XIN)
> 3f(XCIN).
q Use the LDM, STA, etc. instructions to modify the division ratio of the internal clock
φ. (Do not use
read-modify-write instructions such as CLB, SEB, etc.)
q When oscillation of the main clock XIN is restarted, after setting the main clock stop bit to “0”
sufficient time to stabilize oscillation by program.
(2)
In low-speed mode
q The sub-clock XCIN-XCOUT oscillating circuit can not use input clocks externally. Accordingly, make
sure to use an external resonator.
(3)
In stop mode
q Set the interrupt enable bits of timer 1 and timer 2 to the disabled state (“0”) before executing the
STP instruction.
q Oscillation restarts at reset or when an external interrupt is received, but the internal clock
φ is
not supplied to the CPU until timer 2 underflows. It is because that retains time to stabilize
oscillation using a ceramic resonator, etc. Set values for stabilizing oscillation to the timer 1 latch
and the timer 2 latch before executing the STP instruction.
q When using the external interrupt input pin sharing with an I/O port, set “0” (input mode) to the
direction register of a pin to be used before execution of the STP instruction.
q When using an interrupt for release from the stop mode, set the interrupt to the enable state
before execution of the STP instruction.
(4)
In wait mode
q When using an interrupt for release from the wait mode, set the interrupt to the enable state before
execution of the WIT instruction.
q When using the external interrupt input pin sharing with an I/O port, set “0” (input mode) to the
direction register of a pin to be used before execution of the WIT instruction.
Middle-speed
→High-speed
Middle-speed
→Middle-speed
Middle-speed
→Low-speed
High-speed
→Double-speed
High-speed
→MIddle-speed
High-speed
→Low-speed
Low-speed
→High-speed
Low-speed
→Middle-speed
Double-speed
→High-speed
Double-speed
→Middle-speed
Double-speed
→Low-speed
Recommended transition process
Fig. 2.9.12 Program example
Table 2.9.1 Clock switch combination
Low-speed mode
→ Middle/High-speed mode → Double-speed mode switch
LDM xx, CPUM Low-speed mode
→ Middle/High-speed mode switch
NOP
Clock switch timing wait
NOP
(1 to 4 machine cycles are required for switching mode.)
LDM yy, CPUM Switch mode to double-speed
Note: CPUM = CPU mode register (address 003B16)
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