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3874 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
A-D CONVERTER
[A-D/D-A Conversion Register (AD)] 003516
The A-D/D-A conversion register is a register (at reading) that con-
tains the result of an A-D conversion. When reading this register
during an A-D conversion, the previous conversion result is read.
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D/D-A conversion process.
Bits 0 to 2 of this register select specific analog input pins. Bit 3
signals the completion of an A-D conversion. The value of this bit
remains at “0” during an A-D conversion, then changes to “1” when
the A-D conversion is completed. Writing “0” to this bit starts the
A-D conversion. When bit 5, which is the AD external trigger valid
bit, is set to “1”, this bit enables A-D conversion even by a falling
edge of an ADT input. Set “0” (input port) to the direction register
corresponding the ADT pin. Bit 6 is the interrupt source selection
bit. Writing “0” to this bit, A-D converter interrupt request occurs at
completion of A-D conversion. Writing “1” to this bit the interrupt
request occurs at falling edge of an ADT input.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AVSS and VREF by 256, and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P67/AN7 to
P60/AN0 and inputs it to the comparator.
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D/
D-A conversion register. When an A-D conversion is completed,
the control circuit sets the AD conversion completion bit and the
AD conversion interrupt request bit to “1”.
Fig. 62 Block diagram of A-D converter
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to at least 500 kHz during A-D conversion. Use a CPU
system clock dividing the main clock XIN.
Fig. 61 Structure of A-D control register
A-D control register
(ADCON : address 003416)
Analog input pin selection bits
000: P60/AN0
001: P61/AN1
010: P62/AN2
011: P63/AN3
100: P64/AN4
101: P65/AN5
110: P66/AN6
111: P67/AN7
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
VREF input switch bit
0: OFF
1: ON
AD external trigger valid bit
0: AD external trigger invalid
1: AD external trigger valid
Interrupt source selection bit
0: Interrupt request at A-D
conversion completed
1: Interrupt request at ADT
input falling
DA output enable bit
0: DA output disabled
1: DA output enabled
b7
b0
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A-D control circuit
A-D/D-A conversion register
Resistor ladder
AVSS
VREF
Comparator
ADT/A-D interrupt
request
b7
b0
A-D control register
3
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
8
P77/ADT
Data bus