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參數(shù)資料
| 型號： | M38049FFLWG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PBGA64 |
| 封裝： | 6 X 6 MM, 0.65 MM PITCH, PLASTIC, LGA-64 |
| 文件頁數(shù)： | 94/129頁 |
| 文件大?。?/td> | 1721K |
| 代理商： | M38049FFLWG |
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Rev.1.00
Oct 27, 2008
Page 67 of 128
REJ03B0266-0100
3804 Group (Spec.L)
[I2C Status Register (S1)] 001316
The I2C status register (S1: address 001316) controls the I2C-
BUS interface status. The low-order 4 bits are read-only bits and
the high-order 4 bits can be read out and written to.
Set “00002” to the low-order 4 bits, because these bits become
the reserved bits at writing.
Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an
ACK clock occurs, the LRB bit is set to “0”. If ACK is not
returned, this bit is set to “1”. Except in the ACK mode, the last
bit value of received data is input. The state of this bit is changed
from “1” to “0” by executing a write instruction to the I2C data
shift register (S0: address 001116).
Bit 1: General call detecting flag (AD0)
When the ALS bit is “0”, this bit is set to “1” when a general
call* whose address data is all “0” is received in the slave mode.
By a general call of the master device, every slave device
receives control data after the general call. The AD0 bit is set to
“0” by detecting the STOP condition or START condition, or
reset.
* General call: The master transmits the general call address
“0016” to all slaves.
Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the
ALS bit is “0”.
(1) In the slave receive mode, when the 7-bit addressing format
is selected, this bit is set to “1” in one of the following
conditions:
The address data immediately after occurrence of a
START condition agrees with the slave address stored in
the high-order 7 bits of the I2C slave address register.
A general call is received.
(2) In the slave receive mode, when the 10-bit addressing
format is selected, this bit is set to “1” with the following
condition:
When the address data is compared with the I2C slave
address register (8 bits consisting of slave address and
RWB bit), the first bytes agree.
(3) This bit is set to”0” by executing a write instruction to the
I2C data shift register (S0: address 001116) when ES0 is set
to “1” or reset.
Bit 3: Arbitration lost* detecting flag (AL)
In the master transmission mode, when the SDA is made “L” by
any other device, arbitration is judged to have been lost, so that
this bit is set to “1”. At the same time, the TRX bit is set to “0”,
so that immediately after transmission of the byte whose
arbitration was lost is completed, the MST bit is set to “0”. The
arbitration lost can be detected only in the master transmission
mode. When arbitration is lost during slave address transmission,
the TRX bit is set to “0” and the reception mode is set.
Consequently, it becomes possible to detect the agreement of its
own slave address and address data transmitted by another
master device.
The AL bit is set to “0” in one of the following conditions:
Executing a write instruction to the I2C data shift register (S0:
address 001116)
When the ES0 bit is “0”
At reset
* Arbitration lost: The status in which communication as a
master is disabled.
Bit 4: SCL pin low hold bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte
data is transmitted, the PIN bit changes from “1” to “0”. At the
same time, an interrupt request signal occurs to the CPU. The
PIN bit is set to “0” in synchronization with a falling of the last
clock (including the ACK clock) of an internal clock and an
interrupt request signal occurs in synchronization with a falling
of the PIN bit. When the PIN bit is “0”, the SCL is kept in the “0”
state and clock generation is disabled. Figure 65 shows an
interrupt request signal generating timing chart.
The PIN bit is set to “1” in one of the following conditions:
Executing a write instruction to the I2C data shift register (S0:
address 001116). (This is the only condition which the
prohibition of the internal clock is released and data can be
communicated except for the start condition detection.)
When the ES0 bit is “0”
At reset
When writing “1” to the PIN bit by software
The PIN bit is set to “0” in one of the following conditions:
Immediately after completion of 1-byte data transmission
(including when arbitration lost is detected)
Immediately after completion of 1-byte data reception
In the slave reception mode, with ALS = “0” and immediately
after completion of slave address agreement or general call
address reception
In the slave reception mode, with ALS = “1” and immediately
after completion of address data reception
Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this
bit is set to “0”, this bus system is not busy and a START
condition can be generated. The BB flag is set/reset by the SCL,
SDA pins input signal regardless of master/slave. This flag is set
to “1” by detecting the START condition, and is set to “0” by
detecting the STOP condition. The condition of these detecting is
set by the START/STOP condition setting bits (SSC4-SSC0) of
the I2C START/STOP condition control register (S2D: address
001616). When the ES0 bit of the I2C control register (bit 3 of
S1D, address 001416) is “0” or reset, the BB flag is set to “0”.
For the writing function to the BB flag, refer to the sections
“START Condition Generating Method” and “STOP Condition
Generating Method” described later.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| M38049RLSS | 功能描述:DEV EMULATOR CHIP RAM 2KB 64SDIP RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 內(nèi)電路編程器、仿真器以及調(diào)試器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 19/Jul/2010 標準包裝:1 系列:* 類型:* 適用于相關(guān)產(chǎn)品:* 所含物品:* |
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| M3806 BK002 | 制造商:Alpha Wire Company 功能描述:CBL 8COND 18AWG BLK 500' |
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