參數資料
型號： M38049FFLWG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.65 MM PITCH, PLASTIC, LGA-64
文件頁數： 28/129頁
文件大?。?/td> 1721K
代理商： M38049FFLWG
Rev.1.00
Oct 27, 2008
Page 123 of 128
REJ03B0266-0100
3804 Group (Spec.L)
NOTES:
1. When the P45/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”.
2. When the P35/TXD3 P4-channel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”.
Table 33
Switching characteristics
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta =
20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test
conditions
Limits
Unit
Min.
Typ.
Max.
tWH(SCLK1)
tWH(SCLK3)
Serial I/O1, serial I/O3
clock output “H” pulse
width
4.5
≤ VCC ≤ 5.5 V
tC(SCLK1)/2-30, tC(SCLK3)/2-30
ns
4.0
≤ VCC < 4.5 V
tC(SCLK1)/2-35, tC(SCLK3)/2-35
2.7
≤ VCC < 4.0 V
tC(SCLK1)/2-40, tC(SCLK3)/2-40
tWL(SCLK1)
tWL(SCLK3)
Serial I/O1, serial I/O3
clock output “L” pulse
width
4.5
≤ VCC ≤ 5.5 V
tC(SCLK1)/2-30, tC(SCLK3)/2-30
ns
4.0
≤ VCC < 4.5 V
tC(SCLK1)/2-35, tC(SCLK3)/2-35
2.7
≤ VCC < 4.0 V
tC(SCLK1)/2-40, tC(SCLK3)/2-40
td(SCLK1-TxD1)
td(SCLK3-TxD3)
Serial I/O1, serial I/O3
output delay time(1)
4.5
≤ VCC ≤ 5.5 V
140
ns
4.0
≤ VCC < 4.5 V
200
2.7
≤ VCC < 4.0 V
350
tV(SCLK1-TxD1)
tV(SCLK3-TxD3)
Serial I/O1, serial I/O3
output valid time(1)
4.5
≤ VCC ≤ 5.5 V
30
ns
4.0
≤ VCC < 4.5 V
30
2.7
≤ VCC < 4.0 V
30
tr(SCLK1)
tr(SCLK3)
Serial I/O1, serial I/O3
rise time of clock
output
4.5
≤ VCC ≤ 5.5 V
30
ns
4.0
≤ VCC < 4.5 V
35
2.7
≤ VCC < 4.0 V
40
tf(SCLK1)
tf(SCLK3)
Serial I/O1, serial I/O3
fall time of clock output
4.5
≤ VCC ≤ 5.5 V
30
ns
4.0
≤ VCC < 4.5 V
35
2.7
≤ VCC < 4.0 V
40
tWH(SCLK2)
Serial I/O2
clock output “H” pulse
width
4.5
≤ VCC ≤ 5.5 V
tC(SCLK2)/2-160
ns
4.0
≤ VCC < 4.5 V
tC(SCLK2)/2-200
2.7
≤ VCC < 4.0 V
tC(SCLK2)/2-240
tWL(SCLK2)
Serial I/O2
clock output “L” pulse
width
4.5
≤ VCC ≤ 5.5 V
tC(SCLK2)/2-160
ns
4.0
≤ VCC < 4.5 V
tC(SCLK2)/2-200
2.7
≤ VCC < 4.0 V
tC(SCLK2)/2-240
td(SCLK2-SOUT2) Serial I/O2
output delay time
4.5
≤ VCC ≤ 5.5 V
200
ns
4.0
≤ VCC < 4.5 V
250
2.7
≤ VCC < 4.0 V
300
tV(SCLK2-SOUT2)
Serial I/O2
output valid time
4.5
≤ VCC ≤ 5.5 V
0
ns
4.0
≤ VCC < 4.5 V
0
2.7
≤ VCC < 4.0 V
0
tf(SCLK2)
Serial I/O2
fall time of clock output
4.5
≤ VCC ≤ 5.5 V
30
ns
4.0
≤ VCC < 4.5 V
35
2.7
≤ VCC < 4.0 V
40
tr(CMOS)
CMOS
rise time of output(2)
4.5
≤ VCC ≤ 5.5 V
10
30
ns
4.0
≤ VCC < 4.5 V
12
35
2.7
≤ VCC < 4.0 V
15
40
tf(CMOS)
CMOS
fall time of output(2)
4.5
≤ VCC ≤ 5.5 V
10
30
ns
4.0
≤ VCC < 4.5 V
12
35
2.7
≤ VCC < 4.0 V
15
40
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