參數(shù)資料
型號： M38049FFLWG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.65 MM PITCH, PLASTIC, LGA-64
文件頁數(shù)： 104/129頁
文件大小： 1721K
代理商： M38049FFLWG
Rev.1.00
Oct 27, 2008
Page 76 of 128
REJ03B0266-0100
3804 Group (Spec.L)
Precautions when using multi-master I2C BUS inter-
face
(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as
SEB, CLB etc. is executed for each register of the multi-master
I2C-BUS interface are described below.
I2C data shift register (S0: address 001116)
When executing the read-modify-write instruction for this
register during transfer, data may become a value not intended.
I2C slave address registers 0 to 2 (S0D0 to S0D2: addresses
0FF716 to0FF916)
When the read-modify-write instruction is executed for this
register at detecting the STOP condition, data may become a
value not intended. It is because H/W changes the read/write
bit (RWB) at the above timing.
I2C status register (S1: address 001316)
Do not execute the read-modify-write instruction for this
register because all bits of this register are changed by H/W.
I2C control register (S1D: address 001416)
When the read-modify-write instruction is executed for this
register at detecting the START condition or at completing the
byte transfer, data may become a value not intended. Because
H/W changes the bit counter (BC0-BC2) at the above timing.
I2C clock control register (S2: address 001516)
The read-modify-write instruction can be executed for this
register.
I2C START/STOP condition control register (S2D: address
001616)
The read-modify-write instruction can be executed for this
register.
(2) START
condition
generating
procedure
using
multi-master
1. Procedure example (The necessary conditions of the gener-
ating procedure are described as the following 2 to 5.
:
LDA
(Taking out of slave address value)
SEI
(Interrupt disabled)
BBS 5, S1, BUSBUSY (BB flag confirming and branch process)
BUSFREE:
STA S0
(Writing of slave address value)
LDM #$F0, S1
(Trigger of START condition
generating)
CLI
(Interrupt enabled)
:
BUSBUSY:
CLI
(Interrupt enabled)
:
2. Use “Branch on Bit Set” of “BBS 5, S1, -” for the BB flag
confirming and branch process.
3. Use “STA $12, STX $12” or “STY $12” of the zero page
addressing instruction for writing the slave address value to
the I2C data shift register.
4. Execute the branch instruction of above 2 and the store
instruction of above 3 continuously shown the above proce-
dure example.
5. Disable interrupts during the following three process steps:
BB flag confirming
Writing of slave address value
Trigger of START condition generating
When the condition of the BB flag is bus busy, enable
interrupts immediately.
(3) RESTART condition generating procedure
1. Procedure example (The necessary conditions of the gener-
ating procedure are described as the following 2 to 4.)
Execute the following procedure when the PIN bit is “0”
:
LDM #$00, S1
(Select slave receive mode)
LDA
(Taking out of slave address value)
SEI
(Interrupt disabled)
STA S0
(Writing of slave address value)
LDM #$F0, S1
(Trigger of RESTART condition generating)
CLI
(Interrupt enabled)
:
2. Select the slave receive mode when the PIN bit is “0”. Do
not write “1” to the PIN bit. Neither “0” nor “1” is specified
for the writing to the BB bit.
The TRX bit becomes “0” and the SDA pin is released.
3. The SCL pin is released by writing the slave address value
to the I2C data shift register.
4. Disable interrupts during the following two process steps:
Writing of slave address value
Trigger of RESTART condition generating
(4) Writing to I2C status register
Do not execute an instruction to set the PIN bit to “1” from “0”
and an instruction to set the MST and TRX bits to “0” from “1”
simultaneously. It is because it may enter the state that the SCL
pin is released and the SDA pin is released after about one
machine cycle. Do not execute an instruction to set the MST and
TRX bits to “0” from “1” simultaneously when the PIN bit is
“1”. It is because it may become the same as above.
(5) Process of after STOP condition generating
Do not write data in the I2C data shift register S0 and the I2C
status register S1 until the bus busy flag BB becomes “0” after
generating the STOP condition in the master mode. It is because
the STOP condition waveform might not be normally generated.
Reading to the above registers does not have the problem.
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