參數(shù)資料
型號： M37906M8C-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDSO42
封裝： 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁數(shù)： 33/99頁
文件大?。?/td> 1313K
代理商： M37906M8C-XXXFP
62
8168C-MCU Wireless-02/10
AT86RF212
Bit
3
2
1
0
Name
SPI_CMD_MODE
IRQ_MASK_MODE
IRQ_POLARITY
Read/Write
R/W
Reset Value
0
Bit 7 – PA_EXT_EN
Refer to section 9.4.3.
Bit 6 – IRQ_2_EXT_EN
Refer to section 9.5.2.
Bit 5 – TX_AUTO_CRC_ON
If set, register bit TX_AUTO_CRC_ON enables the automatic FCS generation. For
further details refer to section 6.3.
Bit 4 – RX_BL_CTRL
Refer to section 9.6.2.
Bit 3:2 – SPI_CMD_MODE
Refer to section 4.4.1.
Bit 1:0 – IRQ_MASK_MODE, IRQ_POLARITY
Refer to section 4.7.2.
Register 0x17 (XAH_CTRL_1):
The XAH_CTRL_1 register is a control register for Extended Operating Mode.
Table 5-23. Register 0x17 (XAH_CTRL_1)
Bit
7
6
5
4
Name
Reserved
CSMA_LBT_MODE
AACK_FLTR_RES_FT
AACK_UPLD_RES_FT
Read/Write
R/W
Reset Value
0
Bit
3
2
1
0
Name
Reserved
AACK_ACK_TIME
AACK_PROM_MODE
Reserved
Read/Write
R
R/W
R
Reset Value
0
Bit 7 – Reserved
Bit 6 – CSMA_LBT_MODE
Refer to section 6.7.3.
Bit 5 – AACK_FLTR_RES_FT
This register bit shall only be set if AACK_UPLD_RES_FT = 1.
If AACK_FLTR_RES_FT = 1, reserved frame types are filtered like data frames as
specified
in
IEEE 802.15.4-2006.
Reserved
frame
types
are
explained
in
IEEE 802.15.4-2006, section 7.2.1.1.1. Interrupt IRQ_5 (AMI) is issued upon passing
the frame filter, see section 6.2.
相關PDF資料
PDF描述
M37906M4H-XXXSP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP42
M37906M4C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDSO42
M37906M8C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDSO42
M37906M6C-XXXSP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP42
M37906M4C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDSO42
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