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參數(shù)資料
| 型號： | M37905M8C-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP64 |
| 封裝： | 0.750 INCH, 1.78 MM PITCH, PLASTIC, SDIP-64 |
| 文件頁數(shù)： | 88/103頁 |
| 文件大小： | 1402K |
| 代理商： | M37905M8C-XXXSP |
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M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e param
etric
lim
its are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
STANDBY FUNCTION
The standby function provides the stop (hereafter called STP) and
the wait (hereafter called WIT) mode. These modes are used to save
the power dissipation of the system, by making oscillation or system
clock inactive in the case that the CPU needs not be active.
The microcomputer enters the STP or WIT mode by executing the
STP or WIT instruction, and either mode is terminated by acceptance
of an interrupt request or reset.
To terminate the STP or WIT mode by an interrupt request, the inter-
rupt to be used for termination of the STP or WIT mode must be en-
abled in advance to execution of the STP or WIT instruction. The
interrupt priority level of this interrupt needs to be higher than the
processor interrupt priority level (IPL) of the routine where the STP
or WIT instruction will be executed.
Figures 95 shows the bit configuration of the particular function se-
lect register 0, Figure 96 shows the bit configuration of the particular
function select register 1, and Figure 97 shows the bit configuration
of the watchdog timer frequency select register. Setting the STP in-
struction invalidity select bit (bit 0 of the particular function select reg-
ister 0) to “1” invalidates the STP instruction, and the STP instruction
will be ignored. Since the above bit is cleared to “0” after reset is re-
moved, however, the STP instruction is valid.
The STP- or the WIT-instruction-execution status bit (bit 0 or 1 of the
particular function select register 1) is set to “1” by the execution of
the STP or the WIT instruction, and so, after the STP or WIT mode
has been terminated, each bit will indicate that the STP or WIT in-
struction has been executed. Accordingly, each of these bits must be
cleared to “0” by software at termination of the STP or the WIT mode.
Table 11 explains the microcomputer’s operation in the STP and WIT
modes.
STP mode
The execution of the STP instruction makes the oscillation circuit and
PLL circuit inactive. It also makes the following inactive: input clock
fXIN, system clock fsys,
φBIU, φCPU, and peripheral devices’ clocks f1
to f4096, Wf32 and Wf512 with the “L” state, and divide clocks fX16 to
fX128 with the “H” state. In the watchdog timer, “FFF16” is automati-
cally set. As shown in Figure 93, any one of divide clocks fX16 to
fX128, which is selected by the watchdog timer clock source select
bits at STP termination (bits 6 and 7 of the watchdog timer frequency
select register), becomes the watchdog timer’s clock source.
In the STP mode, the A-D converter and watchdog timer, which uses
peripheral devices’ clocks f1 to f4096, Wf32 and Wf512, are inactive. At
this time, timers A and B can be active only in the event counter
mode, and serial I/O communication is active while an external clock
is selected.
The STP mode is terminated by acceptance of an interrupt request
or reset, and the oscillation circuit and PLL circuit restart their opera-
tions. Input clock fXIN, system clock fsys, and peripheral devices’
clocks f1 to f4096, Wf32 and Wf512 are also supplied.
When the STP mode is terminated by reset, supply of
φBIU and φCPU
starts immediately after the oscillation circuit and PLL circuit restart
their operations. Therefore, the reset input must be raised “H” after
the operation-stabilizing time for these circuits has passed.
The following two modes are available in order to terminate the STP
mode by an interrupt:
(1) The watchdog timer is used in order to measure the period from
the operation restart of the oscillation circuit and PLL circuit until
the supply start of
φBIU and φCPU.
(2) The supply of
φBIU and φCPU is started immediately after the op-
eration restart of the oscillation circuit and PLL circuit.
Mode
WIT
System clock
stop select bit
at WIT
Active
(Note 1)
Oscillation
circuit
Operations of function while WIT, STP modes
“0”
fsys,
φ1,
f1 to f4096
Active
STP
Wf32, Wf512
φBIU, φCPU
Inactive
(“L”)
Inactive
(“L”)
Peripheral devices using f1 to f4096, Wf32, Wf512
Timers A, B, Serial I/O, A-D converter: Operation is enabled.
(Watchdog timer: Inactive)
Timers A, B: Operation is enabled only in the event
counter mode.
Serial I/O: Operation is enabled only while an external
clock is selected.
A-D converter: Inactive.
(Watchdog timer: Inactive)
Inactive
(“L”)
Inactive
(“L”)
Inactive
(“L”)
Active
(Note 1)
“1”
Inactive
(“L”)
Inactive
(“L”)
Inactive
(“L”)
Inactive
Timers A, B: Operation is enabled only in the event
counter mode.
Serial I/O: Operation is enabled only while an external
clock is selected.
A-D converter: Inactive.
(Watchdog timer: Inactive)
PLL circuit
Active
(Note 2)
Active
(Note 2)
Inactive
Notes 1: When the external clock input select bit = “1”, the oscillation circuit is inactive. Also, clock input from pin XIN is allowed.
2: When the PLL circuit operation enable bit = “0”, the PLL circuit is inactive.
—
Table 11. Microcomputer’s operation in STP and WIT modes
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| M37905M8C-XXXFP | 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP64 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| M37905T-PRB | 功能描述:DEV POD PROBE FOR M37900T2-RPD-E RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 配件 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 標準包裝:1 系列:- 附件類型:USB 至 1-Wire? RJ11 適配器 適用于相關產(chǎn)品:1-Wire? 設備 產(chǎn)品目錄頁面:1429 (CN2011-ZH PDF) |
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| M37906M4C-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT CMOS MICROCOMPUTER |
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