CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-17
3.2 Chip select wait controller
(7) CS2 control register H
Figure 3.2.7 shows the structure of the CS2 control register H.
Fig. 3.2.7 Structure of CS2 control register H
CS2 control register H (Address 8516)
0 0 0 : 0 byte (Area CS2 is invalid.)
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
0 : Mode 0 (A block can be set to 16-Mbyte space.)
1 : Mode 1 (A block can be set to bank 0.)
(Mode 0)
0 byte (Area CS2 is invalid.)
Do not select.
4 Kbytes
8 Kbytes
Do not select.
Bit name
Bit
Function
At reset
R/W
(Mode 1)
The combination of this bit and the area CS2 bus
cycle select bit 0 selects the bus cycle.
0 : 1
φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2
φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
0
1
2
3
4
5
6
7
Area CS2 block size select bits
Area CS2 bus cycle select bit 1
The value is “0” at reading.
Multiplexed bus select bit
The value is “0” at reading.
Area CS2 setting mode select bit
0
RW
—
RW
—
RW
0 : Separated bus. Input/Output for D0–D7.
1 : Multiplexed bus. LA0/D0–LA7/D7 are input/output
when the external data bus = 8 bits (bit 2 at address
8416 = 1) with area CS2 accessed.
s Area CS2 block size select bit (bits 2 to 0)
These bits select the block size of area CS2. Clearing these bits to “0002” invalidates area CS2.
When the block size has been selected, area CS2 becomes valid and setting for each function of
area CS2 becomes valid, regardless of the CS2 output select bit (bit 7 at address 8416). (See Table
3.2.1.)
s Area CS2 bus cycle select bit 1 (bit 3)
The combination of this bit and the area CS2 bus cycle select bit 0 (bits 0, 1 at address 8416)
selects the bus cycle at access to area CS2. (Refer to section “3.2.2 External bus operations.”)
s Multiplexed bus select bit (bit 5)
Setting this bit to “1” performs the following with the time-sharing method only when area CS2 is
accessed with the external data bus width = 8 bits (Note):
Address (LA0 to LA7) output from pins D0–D7
Data (D0 to D7) input/output
Note: This applies when BYTE = Vcc level or when the external data bus width select bit (bit 2
at address 8416) = 1
s Area CS2 setting mode select bit (bit 7)
This bit selects the setting mode of the block size.
For details of area CS2, see Figures 3.2.10 and 3.2.12.