CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-7
3.2 Chip select wait controller
The chip select wait controller (CSWC) controls the bus cycle at access to the external areas. By CSWC,
the chip select areas (CS0–CS3) of the maximum of 4 blocks can be set in the address space from banks
016 through FE16. (See Figures 3.2.10 to 3.2.12). For each chip select area, the functions listed in Table 3.2.1
can be specified.
For the external areas except for areas CS0–CS3, the functions listed in Table 3.2.1 can also be specified.
Table 3.2.1 Functions of areas CS0 through CS3
Notes 1: When BYTE = Vcc level, the external data bus width is fixed to 8 bits.
2: Burst ROM access is valid only when the external data bus width is 16 bits with instruction prefetched.
3: Burst ROM access and area multiplexed bus access cannot be used at the same time.
4: Valid only when area CS2 is accessed with the 8-bit external data bus width.
5: The address output selection cannot be specified for each area. (Refer to section “3.2.4 Address
output selection.”)
Space where start
address can be set
Block size
Bus cycle
External data bus
width
RDY control
Burst ROM access
(Notes 2, 3)
Recovery cycle
insertion
Area multiplexed bus
access (Note 3)
Address output
selection (Note 5)
CS0
CS1, CS2
CS3
External area except
for CS0 to CS3
Mode 0
Mode 1
Banks 216
to FE16
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
Bus cycle
1
φ + 1φ
1
φ + 2φ
1
φ + 3φ
2
φ + 2φ
2
φ + 3φ
2
φ + 4φ
3
φ + 3φ
3
φ + 4φ
(Selected by bits 0, 1 at address
8016 and bit 3 at address 8116.)
Determined by pin BYTE’s level.
Valid (Selected by bit 2 at address
5F16 and bit 3 at address 8016.)
Available.
Not available.
Available.
Banks 216
to FE16
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
Bus cycle
1
φ + 1φ
1
φ + 2φ
1
φ + 3φ
2
φ + 2φ
2
φ + 3φ
2
φ + 4φ
3
φ + 3φ
3
φ + 4φ
(Selected by bits 0, 1 at addresses
8216, 8416 and bit 3 at addresses
8316, 8516.)
When BYTE = VSS level, 8-bit width or
16-bit width can be selected arbitrary
(Note 1).
Valid (Selected by bit 2 at address
5F16 and bit 3 at addresses 8216,
8416.)
Available.
CS1: Not available.
CS2: Available. (Note 4)
Available.
Bank 016
4 Kbytes,
or 8 Kbytes
Banks 216
to FE16
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
Bus cycle
1
φ + 1φ
1
φ + 2φ
1
φ + 3φ
2
φ + 2φ
2
φ + 3φ
2
φ + 4φ
3
φ + 3φ
3
φ + 4φ
(Selected by bits 0,
1 at address 8616
and bit 3 at address
8716.)
When BYTE = VSS
level, 8-bit width or
16-bit width can be
selected arbitrary
(Note 1).
Valid (Selected by
bit 2 at address
5F16 and bit 3 at
address 8616.)
Available.
Not available.
Available.
Bus cycle
1
φ + 1φ
1
φ + 2φ
1
φ + 3φ
2
φ + 2φ
2
φ + 3φ
2
φ + 4φ
3
φ + 3φ
3
φ + 4φ
(Selected by bits 2,
3 at address 5E16
and bit 0 at address
5F16.)
Determined by pin
BYTE’s level.
Valid (Selected by
bit 2 at address
5F16.)
Not available.
Available.
Not available.
Available.
Mode 0
Mode 1
Bank 016
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes