INPUT/OUTPUT PINS
7902 Group User’s Manual
6-7
6.2 Programmable I/O ports
6.2.3 Selectable functions
In the usage of programmable I/O ports, the following items are selectable:
q Port P0 input level
q Port pins P44–P47 pullup function
Notes 1: For the M37902FxM (power source voltage = 3.3 V±0.3 V), VIH = 0.5Vcc.
2: When MD1 = Vcc and MD0 = Vcc (flash memory parallel I/O mode), pins P44 to P47 and NMI are not pulled up, regardless
of these bits’ contents.
3: When MD1 = Vss and MD0 = Vcc (microprocessor mode), pin CS0 (P44) is not pulled up regardless of this bit’s contents.
0
RW
Port function control register (Address 9216)
b7 b6 b5 b4 b3 b2 b1 b0
0
1
2
3
4
6, 5
7
Bit name
Bit
Function
At reset
R/W
Address/Port switch bits
Port P0 input level select bit
Pins P44–P47 pullup select bit
Fix these bits to “0”.
Pin NMI pullup select bit
0 0 0 : A0 to A23 (16 Mbytes)
0 0 1 : A0 to A21, P06, P07 (4 Mbytes)
0 1 0 : A0 to A19, P04 to P07 (1 Mbytes)
0 1 1 : A0 to A17, P02 to P07 (256 Kbytes)
1 0 0 : A0 to A15, P00 to P07 (64 Kbytes)
1 0 1 : Do not select.
1 1 0 : A0 to A11, P00 to P07, P114 to P117 (4 Kbytes)
1 1 1 : A0 to A7, P00 to P07, P110 to P117 (256 bytes)
b2 b1b0
0 : Pins P44–P47 are pulled up.
1 : Pins P44–P47 are not pulled up (Notes 2, 3).
0 : Pin NMI is pulled up.
1 : Pin NMI is not pulled up (Note 2).
0 : VIH = 0.7 Vcc, VIL = 0.2 Vcc
1 : VIH = 0.43 Vcc (Note 1), VIL = 0.16 Vcc
0
Fig. 6.2.6 Structure of port function control register
(1) Port P0 input level select bit (bit 3)
This bit allows the user to select the input level to port P0 (VIH, VIL). According to the external devices
to be connected with port P0, set this bit’s contents.
(2) Pins P44–P47 pullup select bit (bit 4)
While the voltage level at pin RESET = “L” and after reset, this bit = “0” and pins P44–P47 are pulled
up.
Accordingly, no external pullup resistor is necessary.
By setting this bit to “1,” the pullup state is removed.
When one of the following settings is selected, the pullup state is removed regardless of this bit’s
contents. (The bit’s contents do not change.)
The P44–P47 direction registers are set to “1” (output mode).
The CS0 to CS3 output select bits (bit 7 at addresses 8016, 8216, 8416, 8616) are set to “1”. (By this
setting, the CS0/CS1/CS2/CS3 outputs become enabled.)
Regardless of this bit’s contents;
Pins P44–P47 are not pulled up in the flash memory parallel I/O mode (MD1 = Vcc, MD0 = Vcc).
Pin CS0 (P44) is not pulled up in the microprocessor mode (MD1 = Vss, MD0 = Vcc).
For the flash memory parallel I/O mode, refer to the section on “20.4 Flash memory parallel I/O
mode”.