CONNECTION WITH EXTERNAL DEVICES
7902 Group User’s Manual
3-9
3.2 Chip select wait controller
(2) Processor mode register 1
Figure 3.2.2 shows the structure of the processor mode register 1.
RW
0
(Note 4)
0
Processor mode register 1 (Address 5F16)
0
1
2
3
4
5
6
7
Bit name
Bit
Function
At reset
R/W
b7 b6 b5 b4 b3 b2 b1 b0
0 : Only DPR0 is used.
1 : DPR0 through DPR3 are used.
0 : RDY input is disabled.
(P30 functions as a programmable I/O port pin.)
1 : RDY input is enabled. (P30 functions as pin RDY.)
0 : ALE output is disabled.
(P40 functions as a programmable I/O port pin.)
1 : ALE output is enabled. (P40 functions as pin ALE.)
0 : No recovery cycle is inserted at access to external area.
1 : Recovery cycle is inserted at access to external area.
0 : HOLD input and HLDA output are disabled.
(P43 and P42 function as programmable I/O port pins.)
1 : HOLD input and HLDA output are enabled.
(P43 and P42 function as pins HOLD and HLDA.)
0 : 1 cycle
1 : 2 cycles
0 : 3
φ
1 : 2
φ
(Note 5)
The combination of this bit and the external bus cycle
select bit 0 selects the bus cycle.
0 : 1
φ + 1φ, 1φ + 2φ, 1φ + 3φ, or 2φ + 2φ
1 : 2
φ + 3φ, 2φ + 4φ, 3φ + 3φ, or 3φ + 4φ
(Note 2)
External bus cycle select bit 1
(Note 1)
Direct page register switch bit
RDY input select bit (Note 3)
ALE output select bit (Note 3)
Recovery cycle insert select bit
(Note 3)
HOLD input, HLDA output select
bit (Note 3)
Recovery-cycle-insert number
select bit (Note 6)
Internal ROM bus cycle select bit
(Note 7)
Notes 1: This bit is valid for the external area except for area CSi. Regardless of these bits’ contents, the bus cycle of area CSi is
decided by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 8216, 8416, 8616, and bit 3 at
addresses 8116, 8316, 8516, 8716).
2: After reset, this bit can be set only once. (During the software execution, be sure not to change this bit’s contents.)
3: In the single-chip mode, all of these bits’ functions are disabled regardless of these bits’ contents.
4: When the Vss-level voltage is applied to pin MD0, this bit is “0”; when the Vcc-level voltage is applied to pin MD0, this bit
is “1.”
5: After reset, this bit can be set to “1” only once. Once this bit has been cleared from “1” to “0,” it cannot be back to “1”
again. (Fixed to “0.”)
6: Make sure that a program to be used to change this bit’s contents is allocated in the internal area.
7: In the microprocessor mode, this bit is invalid. This bit is not assigned to the external ROM version. (“0” at reading.)
To reprogram the internal flash memory by using the CPU reprogramming mode, clear this bit to “0.” (Refer to section
“20.2 Flash memory CPU reprogramming mode.”)
Fig. 3.2.2 Structure of processor mode register 1