7902 Group User’s Manual
INTERRUPTS
7-25
b4
0
1
0
1
Fig. 7.10.8 Program example to reserve time required for change of interrupt priority level
Table 7.10.2 Correspondence between number of instructions to be inserted in Figure 7.10.8 and
interrupt priority detection time select bits
[Precautions for interrupts]
1. In order to change the interrupt priority level select bits (bits 0 to 2 at addresses 6E16 to 7F16), 2 to 7
cycles of fsys are required after execution of a write instruction until change of the interrupt priority level.
Therefore, when the interrupt priority level of a certain interrupt source is repeatedly changed in a very
short time, which consists of a few instructions, it is necessary to reserve the time required for the change
by software. Figure 7.10.8 shows a program example to reserve the time required for the change. Note
that the time required for the change depends on the contents of the interrupt priority detection time
select bits (bits 4 and 5 at address 5E16). Table 7.10.2 lists the correspondence between the number of
instructions inserted in Figure 7.10.8 and the interrupt priority detection time select bits.
Interrupt priority detection time select bits (Note)
Interrupt priority level
detection time
7 cycles of fsys
4 cycles of fsys
2 cycles of fsys
Do not select.
b5
0
1
Number of inserted
NOP instructions
7 or more
4 or more
2 or more
Note: We recommend [b5 = “1”, b4 = “0”].
2. When allocating pin INT2 to pin P77, be sure not use pin AN7/ADTRG. Additionally, be sure that the D-A1
output enabled bit (bit 1 at address 9616) = 0 (output disabled).
When allocating pin INT3 to pin P80, be sure that the D-A2 output enabled bit (bit 2 at address 9616) =
0 (output disabled).
When allocating pin INT3 to pin P74, be sure not to use pin AN4.
When allocating pin INT4 to pin P75, be sure not use pin AN5.
; Write instruction for the interrupt priority level select bits
; Inserted NOP instruction (Note)
;
; Write instruction for the interrupt priority level select bits
Note: Except a write instruction for address XX16, any instruction which has the same
cycles as the NOP instruction can also be inserted, instead of the NOP instruction.
For the number of inserted NOP instructions, see Table 7.10.2.
XX: any of 6C to 7F
:
MOVMB 00XXH, #0XH
NOP
MOVMB 00XXH, #0XH
: