FLASH MEMORY VERSION
7902 Group User’s Manual
20-18
20.2 Flash memory CPU reprogramming mode
20.2.5 Software commands
Software commands are described below.
Software commands and data must be read from and written into even-numbered addresses in the user
ROM area, 16 bits at a time. At writing of a command code, the high-order 8 bits (D8 to D15) are ignored.
(1) Read array command
Writing command code “FF16” at the 1st bus cycle pushes the microcomputer into the read array mode.
When an address to be read is input at the next and the following bus cycles, the contents at the
specified address are output to the data bus (D0 to D15), 16 bits at a time.
The read array mode is maintained until another software command is written.
(2) Read status register command
Writing command code “7016” at the 1st bus cycle outputs the contents of the status register to the
data bus (D0 to D7) by a read at the 2nd bus cycle. (See Table 20.2.2.)
(3) Clear status register command
Writing command code “5016” at the 1st bus cycle clears three bits (SR.3 to SR.5) of the status register
to “0.” (See Table 20.2.2.)
Fig. 20.2.2 Setting and Terminate procedures for flash memory CPU reprogramming mode
Jump to the control software transferred in the
above procedure.
(The subsequent procedures will be executed
by the reprogramming control software trans-
ferred in the above procedure.)
User ROM area select bit
← “1”
(Only in the boot mode)
CPU reprogramming mode select bit
← “0”
User ROM area select bit
← “0”
(Only in the boot mode ) (Note 2)
Jump to an arbitrary address in the
internal flash memory area.
The reprogramming control software for the flash
memory CPU reprogramming mode is transferred
to an area other than the internal flash memory.
Software command is executed.
Read array command is executed,
or Flash memory reset bit
← “1”
Flash memory reset bit
← “0”
(Note 1)
CPU reprogramming mode select bit
← “0”
CPU reprogramming mode select bit
← “1”
Notes 1: Before termination of the flash memory CPU reprogramming mode, be sure to execute the read array
command or flash memory reset.
2: When the flash memory CPU reprogramming mode has been terminated with the user ROM area select
bit = “1,” the access to the user ROM area is selected.
Reprogramming control
software
Internal ROM bus cycle select bit
← “0”
(bit 7 at address 5F16)
Interrupt disable flag (I) = “1”
or Interrupt priority level of each interrupt = “0002”
Pin NMI pullup select bit
← “0”
(bit 7 at address 9216)
Single-chip mode,
Memory expansion mode,
or Boot mode