參數(shù)資料
型號: M37702M2-127FP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機
文件頁數(shù): 40/59頁
文件大小: 811K
代理商: M37702M2-127FP
40
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 51 Processor mode register bit configuration
PROCESSOR MODE
The bits 0 and 1 of processor mode register as shown in Figure 51
are used to select any mode of single-chip mode, memory expan-
sion mode, microprocessor mode, and evaluation chip mode.
Ports P3 to P0 and a part of port P4 are used as address, data,
and control signal I/O pins except in single-chip mode.
Figure 52 shows the functions of ports P4 to P0 in each mode.
The external memory area changes when the mode changes.
Figure 53 shows the memory map for each mode.
Refer to Figure 1 for the memory map of the single-chip mode.
The external memory area can be accessed except in single-chip
mode. The accessing of the external memory is affected by the
BYTE pin and the bit 2 (wait bit) of processor mode register.
These will be described next.
BYTE pin
When accessing the external memory, the level of the BYTE pin is
used to determine whether to use the data bus as 8-bit width or
16-bit width.
The data bus width is 8 bits when the level of the BYTE pin is “H”
and port P2 becomes the data I/O pin.
The data bus width is 16 bits when the level of the BYTE pin is “L”
and ports P1 and P2 become the data I/O pins.
When accessing the internal memory, The data bus width is al-
ways 16 bits regardless of the BYTE pin level.
An exclusive mode in the evaluation chip mode allows the BYTE
pin level to be set to 2·V
CC
. In this case, the operation is slightly
different from the above. This is described in the evaluation chip
mode section.
Clock
φ
1
output selection bit
0 : No
φ
1
output
1 :
φ
1
output
Processor mode bit
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Evaluation chip mode
Wait bit
0 : Wait
1 : No Wait
Software reset bit
Reset occurs when this bit is set to 1
Interrupt priority resolusion time selection bit
0 0 : Select 1/f (X
IN
)
14
0 1 : Select 1/f (X
IN
)
8
1 0 : Select 1/f (X
IN
)
4
Test mode bit
This bit must be "0"
7 6 5 4 3 2
0
1
0
Processor mode register
Address
5E
16
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