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參數(shù)資料
| 型號(hào)： | M37643M8-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 36/120頁 |
| 文件大小： | 1253K |
| 代理商： | M37643M8-XXXHP |
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22
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7643 Group
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to
change.
Fig. 17 Structure of interrupt-related registers
Interrupt request register A (address 000216)
IREQA
USB function interrupt request bit
Reserved bit (Undefined at read, “0” at write)
INT0 interrupt request bit
INT1 interrupt request bit
DMAC0 interrupt request bit
DMAC1 interrupt request bit
UART receive buffer full interrupt request bit
UART transmit interrupt request bit
b7
b0
Interrupt polarity select register (address 001116)
IPOL
INT0 interrupt edge select bit
INT1 interrupt edge select bit
Reserved bits (“0” at read/write)
0 : Falling edge active
1 : Rising edge active
b7
b0
0 : Interrupts disabled
1 : Interrupts enabled
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt request register B address (address 000316)
IREQB
UART summing error interrupt request bit
Reserved bit (Undefined at read, “0” at write)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
b7
b0
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt control register A (address 000516)
ICONA
USB function interrupt enable bit
Reserved bit (“0” at read/write)
INT0 interrupt enable bit
INT1 interrupt enable bit
DMAC0 interrupt enable bit
DMAC1 interrupt enable bit
UART receive buffer full interrupt enable bit
UART transmit interrupt enable bit
b7
b0
Interrupt request register C (address 000416)
IREQC
Timer 3 interrupt request bit
Reserved bit (Undefined at read, “0” at write)
Serial I/O interrupt request bit
Reserved bit (Undefined at read, “0” at write)
Key input interrupt request bit
Reserved bit (“0” at read/write)
b7
b0
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt control register B (address 000616)
ICONB
UART summing error interrupt enable bit
Reserved bit (“0” at read/write)
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
b7
b0
0 : Interrupts disabled
1 : Interrupts enabled
Interrupt control register C (address 000716)
ICONC
Timer 3 interrupt enable bit
Reserved bit (“0” at read/write)
Serial I/O interrupt enable bit
Reserved bit (“0” at read/write)
Key input interrupt enable bit
Reserved bit (“0” at read/write)
b7
b0
0 : Interrupts disabled
1 : Interrupts enabled
0
00 00 00
0
00
0
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