參數(shù)資料
型號： M37641M8-XXXHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 85/149頁
文件大小： 1997K
代理商： M37641M8-XXXHP
85
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7641 Group
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
Reset input “L” pulse width
Main clock input cycle time (
Note
)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
INT
0
, INT
1
input cycle time
INT
0
, INT
1
input “H” pulse width
INT
0
, INT
1
input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
Timer T
OUT
delay time
Timer CNTR
0
delay time (Pulse output mode)
Timer CNTR
0
input cycle time (Event counter mode)
Timer CNTR
0
input “H” pulse width (Event counter mode)
Timer CNTR
0
input “L” pulse width (Event counter mode)
Timer CNTR
1
delay time (Pulse output mode)
Timer CNTR
1
input cycle time (Event counter mode)
Timer CNTR
1
input “H” pulse width (Event counter mode)
Timer CNTR
1
input “L” pulse width (Event counter mode)
Serial I/O external clock input cycle time
Serial I/O external clock input “H” pulse width
Serial I/O external clock input “L” pulse width
Serial I/O input setup time (external clock)
Serial I/O input hold time (external clock)
Serial I/O output delay time (external clock)
Serial I/O SRDY valid time (external clock)
Serial I/O internal clock output cycle time
Serial I/O internal clock output “H” pulse width
Serial I/O internal clock output “L” pulse width
Serial I/O input setup time (internal clock)
Serial I/O input hold time (internal clock)
Serial I/O output delay time (internal clock)
t
W
(RESET)
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
t
C
(X
CIN
)
t
WH
(X
CIN
)
t
WL
(X
CIN
)
t
C
(INT)
t
WH
(INT)
t
WL
(INT)
t
C
(CNTRI)
t
WH
(CNTRI)
t
WL
(CNTRI)
t
d
(
φ
-TOUT)
t
d
(
φ
-CNTR
0
)
t
C
(CNTR
E0
)
t
WH
(CNTR
E0
)
t
WL
(CNTR
E0
)
t
d
(
φ
-CNTR
1
)
t
C
(CNTR
E1
)
t
WH
(CNTR
E1
)
t
WL
(CNTR
E1
)
t
C
(SCLK
E
)
t
WH
(SCLK
E
)
t
WL
(SCLK
E
)
t
su
(SRXD-SCLK
E
)
t
h
(SCLK
E
-SRXD)
t
d
(SCLK
E
-STXD)
t
v
(SCLK
E
-SRDY)
t
c
(SCLK
I
)
t
WH
(SCLK
I
)
t
WL
(SCLK
I
)
t
su
(SRXD-SCLK
I
)
t
h
(SCLK
I
-SRXD)
t
d
(SCLK
I
-STXD)
Limits
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
2
41.66
0.4tc(X
IN
)
0.4tc(X
IN
)
200
0.4tc(X
CIN
)
0.4tc(X
CIN
)
200
90
90
200
80
80
200
0.4tc(CNTR
E0
)
0.4tc(CNTR
E0
)
200
0.4tc(CNTR
E1
)
0.4tc(CNTR
E1
)
400
190
180
15
10
166.66
0.5tc(SCLK
I
) – 5
0.5tc(SCLK
I
) – 5
20
5
Typ.
Max.
Symbol
Unit
Table 14 Timing requirements
(Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Note:
Make sure not to exceed 12 MHz of
φ
, in other words, tc(
φ
)
≥
83.33 ns). For example, set bit 7 of the clock control register (CCR) to “0” in the case of
tc(X
IN
)
<
41.66 ns.
Timing Requirements
In Vcc = 5 V
15
15
15
25
26
5
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