參數(shù)資料
型號： M37641M8-XXXHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 113/149頁
文件大?。?/td> 1997K
代理商： M37641M8-XXXHP
113
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
(2) Parallel I/O Mode
The parallel I/O mode is entered by making connections shown in
Figures 96 and 97 and then turning the Vcc power supply (5 V) on.
Pin name
S
i
g
n
a
l
n
a
m
e
I/
O
F
u
n
c
t
i
o
n
V
C
C
,
V
S
S
P
o
w
e
r
s
u
p
p
l
y
i
n
p
u
t
Apply 4.50 V
–
5.25 V to the Vcc pin and 0 V to the Vss pin.
C
N
V
S
S
C
N
V
S
S
Connect this pin to V
cc
.
R
e
s
e
t
i
n
p
u
t
Input
“
L
”
level.
I
R
E
S
E
T
X
I
N
C
l
o
c
k
i
n
p
u
t
Connect a ceramic or crystal resonator between the X
IN
and X
OUT
pins.
When inputting an externally derived clock, input it from X
IN
and leave
X
OUT
open.
X
O
V
C
U
T
C
n
l
o
c
k
o
u
t
p
u
t
A
C
,
A
V
S
S
A
a
l
o
g
p
o
w
e
r
s
u
p
p
l
y
i
n
p
u
t
LPF
x
S
S
LPF
.
3
O
Apply 4.50 V
–
5.25 V to the AVcc pin and 0 V to the AVss pin.
Leave this pin open.
E
t
.
C
a
p
A
d
d
d
r
e
s
s
i
n
p
u
t
These are address AB
0
–
AB
7
input pins.
I
3
V
l
i
n
e
p
o
w
e
r
s
u
p
p
l
y
i
n
p
u
t
I
P
3
0
2
0
t
o
P
2
7
P
B
S
E
L
i
n
p
u
t
This is a BSEL input pin.
P
3
3
P3
4
3
5
3
6
R
P
i
n
p
u
t
This is a RP input pin.
W
In
E
i
n
p
u
t
This is a WE input pin.
P4
0
to P4
4
5
0
t
o
C
E
i
n
p
u
t
OE input
This is a OE input pin.
This is a CE input pin.
O
RY/BY output
This is a RY/BY output pin.
P3
1
3
2
P
P
1
0
0
0
t
o
P
0
7
D
In
a
t
a
I
/
O
These are data DB
0
–
DB
7
input/output pins.
I/O
U
S
S
B
D
+
Input
“
H
”
level.
U
B
D
+
Input
“
H
”
level.
U
B
D
-
U
B
D
-
Input
“
L
”
level.
A
d
r
e
s
s
i
n
p
u
t
These are address AB
8
–
AB
15
input pins.
I
P
t
o
P
1
7
p
u
t
p
o
r
t
P
3
0
I
Input
“
L
”
level.
p
u
t
p
o
r
t
P
3
4
Input
“
L
”
level.
P
P
P3
7
Input port P4
In
p
u
t
p
Input
“
L
”
level.
P
P
5
7
o
r
t
P
5
Input
“
L
”
level.
P6
0
to P6
7
7
0
t
o
8
0
t
o
Input port P6
In
p
u
t
p
In
p
u
t
p
Input
“
L
”
level.
P
P
7
4
o
r
t
P
7
Input
“
L
”
level.
P
P
8
7
o
r
t
P
8
Input
“
L
”
level.
I
I
I
I
I
I
I
I
I
I
I
I
I
Table 28 Description of pin function (Flash Memory Parallel I/O Mode)
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