37
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
Fig. 30 Structure of UART related registers
U
U
A
x
R
M
T
O
x
D
m
o
d
e
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
e
s
0
0
3
0
1
6
,
0
0
3
8
1
6
)
U
A
0
1
A
R
:
φ
:
R
T
c
l
o
c
k
s
e
l
e
c
t
b
i
t
(
C
L
K
)
S
T
C
S
c
G
o
C
c
k
L
p
K
r
U
l
e
s
c
a
l
i
n
g
s
e
l
e
c
t
b
i
t
s
(
P
S
)
b
0
0
1
1
t
o
0
1
a
0
1
a
0
1
A
2
b
0
1
0
1
p
:
:
r
i
:
:
r
i
:
:
R
1
:
:
:
:
b
s
s
y
E
v
O
t
y
P
a
P
a
T
U
U
U
U
i
A
A
A
A
t
t
o
t
o
s
e
e
d
d
e
r
r
ch
R
R
R
R
e
p
p
l
e
n
p
n
a
i
t
y
i
t
y
T
T
T
T
n
b
b
c
p
a
b
c
c
a
r
c
c
c
c
t
h
t
t
s
b
r
i
i
t
y
e
h
e
h
e
a
c
l
l
l
l
o
o
o
o
c
c
c
c
s
k
k
k
k
e
e
d
d
d
d
i
i
i
i
v
v
v
v
t
i
i
i
i
d
d
d
d
b
e
e
e
e
i
t
d
d
d
d
(
S
b
b
b
b
T
y
y
y
y
1
8
3
2
)
2
5
6
S
l
g
l
c
B
1
2
t
i
i
P
t
i
y
t
(
P
M
D
)
a
r
l
t
P
b
c
c
t
e
i
k
k
r
t
i
i
(
n
n
l
e
P
g
g
E
n
N
d
e
g
)
i
n
t
h
s
a
a
b
b
s
l
e
e
e
d
d
e
l
U
l
c
t
b
i
t
b
0
0
1
1
7
b
0
1
0
1
6
:
:
:
:
7
8
9
N
b
b
b
o
i
i
i
t
t
t
s
s
s
a
t
v
a
i
l
a
b
l
e
b
0
b
7
U
U
A
x
R
C
T
O
x
N
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
e
s
0
0
3
3
1
6
,
0
0
3
B
1
6
)
Transmit enable bit (TEN)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (REN)
0: Receive disabled
1: Receive enabled
Transmit initialization bit (TIN)
0: No action.
1: Initializing
Receive initialization bit (RIN)
0: No action.
1: Initializing
Transmit interrupt source select bit (TIS)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
CTS function enable bit (CTS_SEL)
0: CTS function disabled
1: CTS function enabled
RTS function enable bit (RTS_SEL)
0: RTS function disabled
1: RTS function enabled
UART address mode enable bit (AME)
0: Address mode disabled
1: Address mode enabled
b
0
b
7
U
U
A
x
R
S
T
T
x
S
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
e
s
0
0
3
2
1
6
,
0
0
3
A
1
6
)
T
r
0
1
r
0
1
e
0
1
a
0
1
r
a
0
1
v
0
1
u
0
1
e
a
:
:
a
:
:
n
T
T
n
B
B
c
e
:
B
:
B
r
i
t
:
N
:
P
m
:
N
:
F
e
r
:
N
:
O
m
:
(
:
(
s
e
s
m
r
a
r
a
s
m
u
u
i
v
u
u
y
o
a
i
n
o
r
r
u
o
v
m
F
F
E
r
v
i
t
s
s
t
e
f
e
e
f
f
e
f
f
e
e
r
e
r
i
t
g
e
a
m
n
e
e
i
n
E
R
R
e
c
m
m
b
r
r
b
u
r
r
r
o
r
r
y
e
r
r
i
n
e
r
r
r
r
u
g
)
)
d
o
m
i
t
i
t
f
f
u
e
m
f
f
e
m
f
u
r
f
o
r
e
r
r
r
o
o
r
g
r
r
o
o
r
n
e
r
U
U
b
i
p
s
s
e
l
l
l
e
i
i
e
t
t
f
t
e
m
n
c
p
f
l
a
p
m
t
y
g
r
o
p
f
(
T
g
l
e
a
C
r
e
t
e
g
M
s
d
(
T
)
n
n
i
f
f
f
h
h
r
f
i
s
o
T
u
f
l
B
E
)
p
r
p
t
f
t
y
u
y
R
e
l
l
f
l
a
g
(
R
B
F
)
l
l
l
a
P
g
(
P
E
R
)
r
o
r
r
f
F
l
a
g
(
F
E
R
)
e
r
r
f
r
l
o
a
r
O
g
(
O
E
R
)
r
t
e
o
(
(
s
r
r
O
O
(
r
o
f
l
E
E
“
0
r
a
R
R
”
S
g
)
)
a
(
U
U
t
S
E
(
(
r
e
R
S
S
a
)
E
E
d
R
R
/
w
)
)
r
i
=
=
t
0
1
)
R
e
b0
b7
U
U
A
x
R
R
T
T
x
S
C
R
T
S
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
e
s
0
0
3
6
1
6
,
0
0
3
E
1
6
)
Reserved bits (
“
0
”
at read/write)
RTS assertion delay count select bits
b7
b6
b5
b4
0 0 0 0 : No delay; Assertion immediately
0 0 0 1 : 8-bit term assertion at
“
H
”
0 0 1 0 : 16-bit term assertion at
“
H
”
0 0 1 1 : 24-bit term assertion at
“
H
”
0 1 0 0 : 32-bit term assertion at
“
H
”
0 1 0 1 : 40-bit term assertion at
“
H
”
0 1 1 0 : 48-bit term assertion at
“
H
”
0 1 1 1 : 56-bit term assertion at
“
H
”
1 0 0 0 : 64-bit term assertion at
“
H
”
1 0 0 1 : 72-bit term assertion at
“
H
”
1 0 1 0 : 80-bit term assertion at
“
H
”
1 0 1 1 : 88-bit term assertion at
“
H
”
1 1 0 0 : 96-bit term assertion at
“
H
”
1 1 0 1 : 104-bit term assertion at
“
H
”
1 1 1 0 : 112-bit term assertion at
“
H
”
1 1 1 1 : 120-bit term assertion at
“
H
”
b0
0
b7
0
0
0