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參數(shù)資料
| 型號： | M37640M8-XXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE CHIP 8 BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片微機(jī)8位CMOS |
| 文件頁數(shù)： | 57/96頁 |
| 文件大?。?/td> | 1477K |
| 代理商： | M37640M8-XXXFP |
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57
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The
USB Interrupt Enable Registers (USBIE1,
USBIE2)
shown in Figure 1.57 and Figure 1.58, are
used to enable the corresponding interrupt status
conditions that can generate a USB function interrupt.
If the bit to a corresponding interrupt condition is “0”,
that condition will not generate a USB function inter-
rupt. If the bit is a “1”, that condition can generate a
USB function interrupt. Upon reset, all USB interrupt
status conditions are enabled except the USB Sus-
pend Signaling Interrupt (bit 7 of USB Interrupt Enable
Register 2), which is disabled. The USB Reset Inter-
rupt and USB Resume Signaling Interrupt are always
enabled.
INTST0 is set to a “1” by the USB FCU if (in Endpoint
0 IN CSR):
A packet of data is successfully received
A packet of data is successfully sent
IN0CSR3 (DATA_END) bit is cleared (by USB FCU)
IN0CSR4 (FORCE_STALL) bit is set (by the USB
FCU)
IN0CSR5 (SETUP_END) bit is set (by the USB FCU)
Fig. 1.57. USB Interrupt Enable Register 1 (USBIE1)
Fig. 1.58. USB Interrupt Enable Register 2 (USBIE2)
INTEN7
INTEN5
INTEN4
INTEN2
Reserved
MSB
7
LSB
0
Address: 0054
16
Access: R/W
Reset: FF
16
INTST0
INTEN6
INTEN3
INTEN0
USB Endpoint 0 Interrupt Status Flag (bit 0)
Bit 1
Reserved (Read/Write “0”)
INTST2
INTST3
INTST4
INTST5
INTST6
INTST7
USB Endpoint 1 IN Interrupt Enable Bit (bit 2)
USB Endpoint 1 OUT Interrupt Enable Bit (bit 3)
USB Endpoint 2 IN Interrupt Enable Bit (bit 4)
USB Endpoint 2 OUT Interrupt Enable Bit (bit 5)
USB Endpoint 3 IN Interrupt Enable Bit (bit 6)
USB Endpoint 3 IN Interrupt Enable Bit (bit 7)
0: Interrupt disabled
1: Interrupt enabled
INTST2, INTST4, INTST6 or INTST8 is set to a “1” by
USB FCU if (in Endpoint x IN CSR):
A packet of data is successfully sent
INXCSR1 (UNDER_RUN) bit is set (by USB FCU)
INTST3, INTST5, INTST7 or INTST9 is set to a “1” by
USB FCU if (in Endpoint xOUT CSR):
A packet of data is successfully received
OUTXCSR1 (OVER_RUN) bit is set (by USB FCU)
OUTXCSR4 (FORCE_STALL) bit is set (by USB
FCU)
INTST12 is set to a “1” by the USB FCU if an overrun
or underrun condition occurs in any of the endpoints.
INTST13 is set to a “1” by the USB FCU if USB reset
signaling from the host is received. All USB internal
registers other than this bit are reset to their default
values when the USB reset is received.
INTST14 is set to a “1” by the USB FCU when the
USB FCU is in the suspend state and non-idle signal-
ing on D+/D- is received.
INTST15 is set to a “1” by the USB FCU when D+/D-
are in the idle state for more than 3ms.
INTEN8
INTEN9
USB Endpoint 4 IN Interrupt Enable Bit (bit 0)
USB Endpoint 4 Out Interrupt Enable Bit (bit 1)
Bit 3:2
Reserved (Read/Write “0”)
INTST12
USB Overrun/Underrun Interrupt Enable Bit (bit 4)
Bit 5
Bit 6
Reserved (Read/Write “1”)
Reserved (Read/Write “0”)
INTEN15
USB Suspend Signaling Interrupt Enable Bit (bit 7)
0: Interrupt disabled
1: Interrupt enabled
INTEN15
Reserved
INTEN12
Reserved
INTEN9
MSB
7
LSB
0
Address: 0055
16
Access: R/W
Reset: 33
16
Reserved
Reserved
INTEN8
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