參數(shù)資料
型號: M37640M8-XXXFP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE CHIP 8 BIT CMOS MICROCOMPUTER
中文描述: 單片微機8位CMOS
文件頁數(shù): 20/96頁
文件大小: 1477K
代理商: M37640M8-XXXFP
20
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.14.1.4 Port P5
Port 5 is an 8-bit general purpose I/O port that can be
configured to access special second functions. The
port can be set up in any configuration in all three pro-
cessor modes.
Port P5
0
This pin is multiplexed with the XC
in
clock input.
When the XC
in
clock is activated, the pin’s I/O is dis-
abled.
Port P5
1
This pin is multiplexed with the XC
out
clock output
and the Timer 1/2 pulse output. When the XC
in
clock
is activated, the pin’s I/O is disabled. If XC
in
is not be-
ing used as a system clock or XC
out
oscillation is dis-
abled, the pin can be configured as the Timer 1/2
pulse output pin. This feature is configured in the
Timer123 mode register as described in section 1.17.
Port P5
2
- P5
7
These pins are multiplexed with control pins for the
bus interface control block. P5
2
acts as OBF
0
output
to a Master CPU when DBBC00 is “1”.
P5
3
acts as IBF
0
output to a Master CPU when
DBBC01 is “1”.
P5
4
-P5
7
act as input control signals from a Master
CPU when DBBC06 is “1”. The table featured in Fig-
ure 1.17 shows the bus interface control signal that
corresponds to each pin.
Fig. 1.17. Port P5 Block Diagram
Direction Register
Data Bus
Port Latch
CPMA4
CPMA4
CPMA4
XC
in
Input
Direction Register
Data Bus
Port Latch
T
out
Enable Bit
Timer 1/2 Output
Direction Register
Data Bus
Port Latch
DBBC00
OBF
0
Direction Register
Data Bus
Port Latch
DBBC01
IBF
0
Port 5
4
- P5
7
Function
Pin
Function
P5
4
S
0
P5
5
A
0
P5
6
R(E)
P5
7
W(R/W)
Data Bus
Port Latch
see table
for function
Directi
Register
DBBC06
DBBC06
on
Port P5
0
Port P5
1
Port 5
2
Port P5
3
Port P5
4
- P5
7
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