參數(shù)資料
型號(hào)： M37640M8-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE CHIP 8 BIT CMOS MICROCOMPUTER
中文描述： 單片微機(jī)8位CMOS
文件頁數(shù)： 47/96頁
文件大?。?/td> 1477K
代理商： M37640M8-XXXFP
47
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.19.5 Interrupts
The transmit and receive interrupts are generated un-
der the conditions described below. The generation of
the receive interrupts differs when UART Address
mode is enabled.
1.19.5.1 Transmit interrupts
The UART generates a Transmit interrupt to the CPU
core. The source of the Transmit interrupt is select-
able by setting TIS.
If TIS = “0”, the Transmit interrupt is generated when
the transmit buffer register becomes empty (that is,
when TBE flag set).
If TIS = “1”, the Transmit interrupt is generated after
the last bit is sent out of the transmit shift register and
no data has been written to the transmit buffer or CTS
handshaking is enabled and CTSx is high (that is,
when TCM flag set).
1.19.5.2 Receive Interrupts
The UART generates the Receive Buffer Full (RBF)
and Receive Error Sum (SER) interrupts to the CPU
core when receiving.
The RBF interrupt is generated when a receive opera-
tion completes and a receive error is not generated.
The SER interrupt is generated when an overrun, fram-
ing or parity error occurs.
1.19.6 Clear-to Send (CTSx) and Request-to-Send
(RTSx) Signals
The UART, as a transmitter, can be configured to rec-
ognize the Clear-to-Send (CTSx) input as a
handshaking signal. As a receiver, the UART can be
configured to generate the Request-to-Send (RTSx)
handshaking signal.
1.19.6.1 Clear-to-Send (CTSx) Input
CTS handshaking is enabled by setting the Clear-to-
Send Enable Bit (CTS_SEL, bit 5 of UxCON) to a “1”.
If CTS handshaking is enabled, when TEN is a “1” and
the low-order byte of the transmit buffer (UxTRB1) is
loaded, the UART begins the transmission process
when the CTSx pin is asserted (low input). After begin-
ning a send operation, the UART does not stop
sending until the transmission is completed, even if
CTSx is deasserted (high input). If TEN is cleared to
“0”, the UART will not stop transmitting and the port
pins will remain under the control of the UART until
the end of the transmission. If CTS handshaking is
disabled and TEN is a “1”, the UART begins the trans-
mission process as soon as data is available in the
low-order byte of the transmit buffer (UxTRB1). Figure
1.47 shows a timing example for CTSx.
1.19.6.2 Request-to-Send (RTSx) Output
RTS handshaking is enabled by setting the Request-
to-Send Enable Bit (RTS_SEL, bit 6 of UxCON) to a
“1”. When RTS handshaking is enabled, the UART
drives the RTSx output low or high based on the fol-
lowing conditions:
Assertion conditions (driven low):
The Receive Enable Bit (REN) is set to a “1”.
Receive operation has completed with the reception of
the last stop bit, REN is still a “1”, and the program-
mable assertion delay has expired.
De-assertion conditions (driven high):
A valid start bit is detected and REN is a “1”.
REN is cleared to a “0” before a receive operation is in
progress.
Receive operation has completed and REN is a “0”.
UART Receiver is initialized (RIN is set to a “1”).
The delay time from the reception of the last stop bit
to the re-assertion of RTSx is programmable. The
amount of delay is selected by setting the RTS Asser-
tion Delay Count Bits (RTS 3~0, bits 3 to 0 of
UxRTSC) (see Figure 1.48 ). The time can be from no
delay to 120 bit-times, with the delay beginning from
the middle of the last stop bit. If a start bit is detected
before the assertion delay has expired, the delay
countdown is stopped and the RTSx pin remains high.
A full assertion delay countdown will begin again once
the last stop bit of the incoming data has been re-
ceived. See Figure 1.47 for a timing example for
RTSx.
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