參數(shù)資料
型號： M37640M8-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE CHIP 8 BIT CMOS MICROCOMPUTER
中文描述： 單片微機8位CMOS
文件頁數(shù)： 30/96頁
文件大?。?/td> 1477K
代理商： M37640M8-XXXFP
30
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.17 TIMERS
This device has five built-in timers: Timer X, Timer Y,
Timer 1, Timer 2, and Timer 3.
The contents of the timer latch, corresponding to
each timer, determine the divide ratio. The timers can
be read or written at any time. However, the read and
write operations on the high and low-order bytes of
the 16-bit timers (Timer X and Y) must be performed
in a specific order.
The timers are all down count timers; when the count
of a timer reaches 00
16
(0000
16
for Timer X and Y),
an underflow occurs at the next count pulse and the
contents of the corresponding timer reload latch are
reloaded into the timer. When a timer underflows, the
interrupt request bit corresponding to that timer is set
to a “1”.
The divide ratio of a timer is given by 1/(n + 1), where
n is the value written to the timer. When the STP in-
struction is executed or RESET is asserted, 01
16
is
loaded into Timer 2 and the Timer 2 reload latch, and
FF
16
is loaded into Timer 1 and the Timer 1 reload
latch.
Figure 1.32 is a block diagram of the five timers.
Fig. 1.32. Block diagram of Timers X, Y, 1, 2, and 3
Timer X Divider
(1/
)
n
=8, 16, 32, 64
Timer Y Divider
(1/
)
SCSGCLK
TXM2,1
TYM3,2
Φ
1/8
Timer XL Latch(8)
Timer XL (8)
Timer XH Latch(8)
Timer XH (8)
TXM0
Timer X Interrupt Request
CNTR0 Interrupt Request
10
00
01
TXM7
TXM5,4
11
TXM6
TXM3
1
0
1
TXM6
TXM5, 4 = 01
0
1
Q
Q
T
TXM5,4= 01
Rising Edge Detector
Falling Edge Detector
TYM5,4= 11
Tor 11
Timer YL Latch(8)
Timer YL (8)
Timer YH Latch(8)
Timer YH (8)
TYM0
TYM7
TYM5,4
00
01
11
10
0
TYM6
TYM= 1 & TYM5, 4 = 00
1
TYM6
0
1
Q
Q
T
TYM1= 11 and TYM5,4 = 0
00
01
10
S
TYM5,4
11
Timer Y Interrupt Request
CNTR1 Interrupt Request
0
1
T123M5
T123M6= 1
T123M6= 1
Timer 2 Latch(8)
Timer 2 (8)
T123M7
IntTimer 2
Timer 3 Latch(8)
Timer3 (8)
Interrupt Request
1
Timer 1 Latch(8)
Timer 1 (8)
T123M7
T123M3
T123M4
1
0
0
Q
Q
T
S
TOUT
CNTR1
CNTR0
XC
in
/2
T123M2
0
1
0
T123M1
IntTimer 1
0
1
T123M6 =1
Q
Q
T
S
T123M5
1
0
T123M0
Φ
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