參數(shù)資料
型號: M37640M8-126FP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 7/96頁
文件大?。?/td> 1477K
代理商: M37640M8-126FP
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7
1.10 CPU MODE REGISTERS
This device has two CPU mode registers:
CPU Mode Register A (CPMA)
CPU Mode Register B (CPMB)
These registers control the processor mode, clock,
slow memory wait and other CPU functions. The bit
representation of each register is described in Figure
1.5 and Figure 1.6.
Fig. 1.5. CPU Mode Register A (CPMA)
Fig.1.6. CPU Mode Register B (CPMB)
CPMA7
CPMA5
CPMA4
Reserved
CPMA2
CPMA1
CPMA0
MSB
7
LSB
0
Address: 0000
16
Access: R/W
Reset: OC
16
CPMA6
CPMA0,1
Processor Mode Bits (bits 1,0)
Bit 1
0
0
1
1
Stack Page Selection Bit (bit 2)
0:
In page 0 area
1:
In page 1 area
Reserved (Read/Write “1”)
Clock XC
- XC
out
Stop Bit (bit 4)
0: Stop
1: Oscillator
CPMA5 Clock X
- X
Stop Bit (bit 5)
0: Oscillator
1: Stop
CPMA6 Internal Clock Selection Bit (bit 6)
0: External Clock
1: f
CPMA7
External Clock Selection Bit (bit 7)
0: X
in
- X
1: XC
in
- XC
out
Bit 0
0: Single-Chip Mode
1: Memory Expansion Mode
0: Microprocessor Mode
1: Not Used
CPMA2
CPMA3
CPMA4
CPMB0,1
Slow Memory Wait Bits (bits 1,0)
Bit 1
0
0
1
1
Slow Memory Mode Bit (bit 3,2)
Bit 3
0
0
1
1
CPB4
Expanded Data Memory Access Bit (bit 4)
0:EDMA output disabled (64 Kbyte data access area)
1:EDMA output enabled (greater than 64 Kbytes data access area)
CPMB5
Hold Function Enable Bit (bit 5)
0:HOLD Function Disabled
1:HOLD Function Enabled
CPMB6
Reserved (Read/Write “0”)
CPMB7
Reserved (Read/Write “1”)
Bit 0
0: No Wait
1: One time wait
0: Two time wait
1: Three time wait
CPMB2,3
Bit 2
0: Software wait
1: Not used
0: Fixed wait by RDY pin L
1: Extended RDY wait
CPMB5
CPMB4
CPMB2
CPMB1
CPMB0
MSB
7
LSB
0
Address: 0001
16
Access: R/W
Reset: 83
16
CPMB3
Reserved
Reserved
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