參數(shù)資料
型號: M37640M8-126FP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 17/96頁
文件大?。?/td> 1477K
代理商: M37640M8-126FP
17
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.14 INPUT AND OUTPUT PORTS
Table 1.5. Input and Output Ports
Pin
Name
Input/
Output
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
I/O
Format
CMOS I/O
port
CMOS I/O
port
CMOS I/O
port
CMOS I/O
port
Non-Port
Function
Related
SFR’s
Ref. Number
P0
0
P0
7
Port 0
Address Bus
CPU Mode Register
Fig. 1.15
P1
0
P1
7
Port 1
Address Bus
CPU Mode Register
Fig. 1.15
P2
0
P2
7
Port 2
Data Bus
CPU Mode Register
Fig. 1.15
P3
0
P3
7
Port 3
Control signal I/O
CPU Mode Register
Fig. 1.15
P4
0
P4
1
Expanded Data Memory
Access
External Interrupt Input
(INT0)
External Interrupt Input
(INT1)
External Interrupt Input
(CNTR0)
External Interrupt Input
(CNTR1)
X
cin
CPU Mode Register
Fig. 1.16
Interrupt Edge
Selection Register
Interrupt Edge
Selection Register
Timer X Mode
Register
Timer Y Mode
Register
CPU Mode Register
CPU Mode Register
or T123 Mode
Register
MBI Interface
MBI Interface
MBI Interface
MBI Interface
MBI Interface
MBI Interface
MBI Interface
Fig. 1.16
P4
2
Fig. 1.16
P4
3
Fig. 1.16
P4
4
Port 4
Input/output,
individual bits
CMOS I/O
port
Fig. 1.16
P5
0
Fig. 1.17
Fig. 1.17
P5
1
X
cout
or T
out
P5
2
P5
3
P5
4
P5
5
P5
6
P5
7
OBF
0
Output
IBF
0
Output
S
0
Input
A
0
Input
R(E) Input
W(R/W) Input
Fig. 1.17
Fig. 1.17
Fig. 1.17
Fig. 1.17
Fig. 1.17
Fig. 1.17
Fig. 1.18
Port 5
Input/output,
individual bits
CMOS I/O
port
P6
0
P6
7
P7
0
P7
1
P7
2
P7
3
P7
4
Port 6
Input/output,
individual bits
CMOS I/O
port
Master CPU data bus
SOF Output
HOLD
S
1
Input
IBF
1
Output
OBF
1
Output
USB Interface
CPU Mode Register
MBI Interface
MBI Interface
MBI Interface
UART Mode
Register/SIO Mode
Register
UART Mode
Register/SIO Mode
Register
UART Mode
Register/SIO Mode
Register
UART Mode
Register/SIO Mode
Register
UART Mode
Register
UART Mode
Register
UART Mode
Register
UART Mode
Register
Fig. 1.19
Fig. 1.19
Fig. 1.19
Fig. 1.19
Fig. 1.19
Fig. 1.20
Port 7
Input/output,
individual bits
CMOS I/O
port
P8
0
UTXD2/SRDY
P8
1
URXD2/SCLK
Fig. 1.20
P8
2
CTS2/STXD
Fig. 1.21
P8
3
RTS2/SRXD
Fig. 1.21
P8
4
UTXD1
Fig. 1.21
P8
5
URXD1
Fig. 1.22
P8
6
CTS1
Fig. 1.22
P8
7
Port 8
Input/output,
individual bits
CMOS I/O
port
RTS1
Fig. 1.22
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