參數(shù)資料
型號(hào)： M37640M8-126FP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 53/96頁(yè)
文件大?。?/td> 1477K
代理商： M37640M8-126FP
53
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The following outlines the operation sequence for an
IN endpoint used to communicate rate feedback infor-
mation:
1. Set MAXP > 1/2 of the endpoint’s FIFO size
2. Set the INTPT bit of the IN CSR
3. Flush the old data in the FIFO
4. Load interrupt status information and set the
IN_PKT_RDY bit in the IN CSR
5. Repeat steps 3 and 4 for all subsequent interrupt
status updates.
In real applications, if an interrupt endpoint is used for
rate feedback, the function always has data to send
back to the host, even if that data conveys that every-
thing is ‘fine’. Therefore the device never NAKs an IN
token from the host. The device always sends out the
data in the FIFO in response to an IN token irrespec-
tive of the IN_PKT_RDY bit.
1.21.3.2 OUT (Receive) FIFOs
The USB FCU writes data to the endpoint’s OUT
FIFO location specified by the FIFO write pointer,
which automatically increments by one after a write.
When the USB FCU has successfully received a data
packet, it sets the OUT_PKT_RDY bit to a “1” in the
OUT CSR. The CPU/DMAC should only read data
from the OUT FIFO if the OUT_PKT_RDY bit of the
OUT CSR is a “1”, with the exception of endpoint 1
(see detailed description below).
Endpoint 0 OUT FIFO Operation:
The USB FCU sets the OUT_PKT_RDY bit to a “1”
after it has successfully received a packet of data
from
the
host.
The
SERVICED_OUT_PKT_RDY to a “1” to clear the
OUT_PKT_RDY bit after the packet of data has been
unloaded from the OUT FIFO by the CPU.
Endpoint 1-4 OUT FIFO Operation when
AUTO_CLR (bit 7 of OUT CSR) = “0”:
MAXP > 1/2 of the OUT FIFO size:
The USB FCU
sets the OUT_PKT_RDY bit to a “1” after it has suc-
cessfully received a packet of data from the host.
The CPU writes a “0” to the OUT_PKT_RDY bit af-
ter the packet of data has been unloaded from the
OUT FIFO by the CPU/DMAC.
MAXP <= 1/2 of the OUT FIFO size:
The USB
FCU sets the OUT_PKT_RDY bit to a “1” after it
has successfully received a packet of data from the
host. The CPU writes a “0” to the OUT_PKT_RDY
bit after the packet of data has been unloaded from
CPU
sets
bit
the OUT FIFO by the CPU/DMAC. In this configura-
tion, the FIFO can hold up to two data packets at
the same time for back-to-back reception. There-
fore, the OUT_PKT_RDY bit will remain set after
the CPU writes a “0” to it if there is another packet
in the OUT FIFO.
Endpoint 1-4 OUT FIFO Operation when
AUTO_CLR (bit 7 of OUT CSR) = “1”:
MAXP > 1/2 of the OUT FIFO size:
The USB FCU
sets the OUT_PKT_RDY bit to a “1” after it has suc-
cessfully received a packet of data from the host.
The USB FCU clears the OUT_PKT_RDY bit to a
“0” automatically when the number of bytes of data
equal to the MAXP (maximum packet size) have
been unloaded from the OUT FIFO by the CPU/
DMAC.
MAXP <= 1/2 of the OUT FIFO size:
The USB
FCU sets the OUT_PKT_RDY bit to a “1” after it
has successfully received a packet of data from the
host. The USB FCU clears the OUT_PKT_RDY bit
to a “0” automatically when the number of bytes of
data equal to the MAXP (maximum packet size)
have been unloaded from the OUT FIFO by the
CPU/DMAC. In this configuration, the FIFO can
hold up to two data packets at the same time for
back-to-back
reception.
OUT_PKT_RDY bit will remain set after one packet
(size equal to MAXP) of data has been unloaded if
there is another packet in the OUT FIFO.
A software flush causes the USB FCU to act as if a
packet has been unloaded from the OUT FIFO. If
there is one packet in the OUT FIFO, a flush will
cause the OUT FIFO to be empty. If there are two
packets in the OUT FIFO, a flush will cause the older
packet to be flushed out from the OUT FIFO.
Special case for OUT Endpoint 1:
In addition to the OUT FIFO operations described
above, the DMAC can also start unloading the OUT
FIFO as soon as there is data in it (byte-by-byte
transfer). This feature should only be used with ISO
transfers. See DMAC section for details.
Therefore,
the
相關(guān)PDF資料
PDF描述
M37640E8 SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
M37641F8-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37641F8-XXXHP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37641M8-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37641M8 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M37640M8-XXXFP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE CHIP 8 BIT CMOS MICROCOMPUTER
M37641F8E8-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37641F8FP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37641F8FP#U0 功能描述:IC 740 MCU FLASH 32K 80QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/7600 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲(chǔ)器容量:40KB（20K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
M37641F8HP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*