參數(shù)資料
型號(hào)： M37640M8-126FP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 69/96頁(yè)
文件大?。?/td> 1477K
代理商： M37640M8-126FP
69
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 1.82. DMAC Index and Status Mode Register (DMAIS)
Fig. 1.83. DMAC Channel x Mode Register 1 (DMAxM1)
DxSRID
DMAC Channel x Source Register Increment/Decrement Select Bit (bit 0)
0:
Increment after transfer
1:
Decrement after transfer
DMAC Channel x Source Register Increment/Decrement Enable Bit (bit 1)
0:
Increment/Decrement disabled (No change after transfer)
1:
Increment/Decrement enabled
DMAC Channel x Destination Resgister Increment/Decrement Select Bit (bit 2)
0:
Increment after transfer
1:
Decrement after transfer
DMAC Channel x Destination Register Increment/Decrement Enable Bit (bit 3)
0:
Increment/Decrement disabled (No change after transfer)
1:
Increment/Decrement enabled
DMAC Channel x Data Write Control Bit (bit 4)
0:
Write data in reload latches and registers
1:
Write data in reload latches only
DMAC Channel x Disable After Count Register Underflow Enable Bit (bit 5)
0:
Channel x not disabled after count register underflow
1:
Channel x disabled after count register underflow
DMAC Channel x Register Reload Bit (bit 6)
0:
No action (Bit is always read as “0”)
1:
Setting to “1” causes the source, destination, and transfer count
registers of channel x to be reloaded
DMAC Channel x Transfer Mode Selection Bit (bit 7)
0:
Single-byte transfer mode
1:
Burst transfer mode
DxSRCE
DxDRID
DxDRCE
DxDWC
DxDAUE
DxRLD
DxTMS
DxTMS
DxDAUE
DxDWC
DxDRCE
DxDRID
DxSRCE
DxSRID
MSB
LSB
Address: 0040
16
Access: R/W
DxRLD
DCI
DRLDD
DTSC
DISFI
DIUF
DOSFI
DOUF
MSB
7
LSB
0
Address: 003F
16
Access: R/W
Reset: 00
16
Reserved
D0UF
DMAC Channel 0 Count Register Underflow Flag (bit 0)
0: Channel 0 transfer count register underflow has not occurred
1: Channel 0 transfer count register underflow has occured
DMAC Channel 0 Suspend (dur to interrupt service request) Flag (bit 1)
0: Channel 0 transfer has not been suspended
1: Channel 0 transfer has been suspended
DMAC Channel 1 Count Register Underflow Flag (bit 2)
0: Channel 1 transfer count register underflow has not occurred
1: Channel 1 transfer count register underflow has occurred
DMAC Channel 1 Suspend (due to interrupt service request ) Flag (bit 3)
0: Channel 1 transfer has not been suspended
1; Channel 1 transfer has been suspended
DMAC Transfer Suspend Control Bit (bit 4)
0: Only burst transfers are suspended during interrupt servicing
1: Both burst and single-byte transfers are suspended during
interrupt servicing
DMAC Register Reload Disable Bit (bit 5)
0: Reload of source and destination registers of both channels
enabled
1: Reload of source and destination registers of both channels
disabled
Reserved (Read/Write “0”)
Channel Index Bit (bit 7)
0: Channel 0 mode,source, destination, and transfer count registers
accessible
1: Channel 1 mode, source, destination, and transfer count registers
accessible
D0SFI
D1UF
D1SFI
DTSC
DRLDD
Bit 6
DCI
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