參數(shù)資料
型號(hào)： M37640M8-126FP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 52/96頁
文件大?。?/td> 1477K
代理商： M37640M8-126FP
52
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.21.3.1 IN (Transmit) FIFOs
The CPU/DMA writes data to the endpoint’s IN FIFO
location specified by the FIFO write pointer, which au-
tomatically increments by “1” after a write. The CPU/
DMA should only write data to the IN FIFO if the
IN_PKT_RDY bit of the IN CSR is a “0”.
Endpoint 0 IN FIFO Operation:
The CPU writes a “1” to the IN_PKT_RDY bit after it
finishes writing a packet of data to the IN FIFO. The
USB FCU clears the IN_PKT_RDY bit after the
packet has been successfully transmitted to the host
(ACK is received from the host) or the SETUP_END
bit of the IN CSR is set to a “1”.
Endpoint 1-4 IN FIFO Operation when AUTO_SET
(bit 7 of IN CSR) = “0”:
MAXP > 1/2 of the IN FIFO size:
The CPU writes a
“1” to the IN_PKT_RDY bit after the CPU/DMAC
finishes writing a packet of data to the IN FIFO. The
USB FCU clears the IN_PKT_RDY bit after the
packet has been successfully transmitted to the
host (ACK is received from the host).
MAXP <= 1/2 of the IN FIFO size:
The CPU writes
a “1” to the IN_PKT_RDY bit after the CPU/DMAC
finishes writing a packet of data to the IN FIFO. The
USB FCU clears the IN_PKT_RDY bit as soon as
the IN FIFO is ready to accept another data packet.
(The FIFO can hold up to two data packets at the
same time in this configuration for back-to-back
transmission). Since the set and the clear opera-
tions could be as fast as 83ns (one 12MHz clock
period) apart from each other, the set may be trans-
parent to the user.
Endpoint 1-4 IN FIFO Operation when AUTO_SET
(bit 7 of IN CSR) = “1”:
MAXP > 1/2 of the IN FIFO size:
When the number
of bytes of data equal to the MAXP (maximum
packet size) is written to the IN FIFO by the CPU/
DMAC, the USB FCU sets the IN_PKT_RDY bit to
a “1” automatically. The USB FCU clears the
IN_PKT_RDY bit after the packet has been suc-
cessfully transmitted to the host (ACK is received
from the host).
MAXP <= 1/2 of the IN FIFO size:
When the num-
ber of bytes of data equal to the MAXP (maximum
packet size) is written to the IN FIFO by the CPU/
DMAC, the USB FCU sets the IN_PKT_RDY bit to
a “1” automatically. The USB FCU clears the
IN_PKT_RDY bit as soon as the IN FIFO is ready
to accept another data packet. (The FIFO can hold
up to two data packets at the same time in this con-
figuration for back-to-back transmission). Since the
set and the clear operations could be as fast as
83ns (one 12MHz clock period) apart from each
other, the set may be transparent to the user.
A software or a hardware flush causes the USB FCU
to act as if a packet has been successfully transmit-
ted out to the host. If there is one packet in the IN
FIFO, a flush will cause the IN FIFO to be empty. If
there are two packets in the IN FIFO, a flush will
cause the older packet to be flushed out from the IN
FIFO. A Flush will also update the IN FIFO status bits
IN_PKT_RDY and TX_NOT_EMPTY.
The status of endpoint 1-4 IN FIFOs for both of the
above cases can be obtained from the IN CSR of the
corresponding IN FIFO as shown in Table 1.8.
Table 1.8. Endpoint 1_4 IN FIFO Status
Interrupt Endpoints:
Any endpoint can be used for interrupt transfers. For
normal interrupt transfers, the interrupt transactions
behave the same as bulk transactions, i.e.; no special
setting is required. The IN endpoints may also be
used to communicate rate feedback information for
certain types of isochronous functions. This is done
by setting the INTPT bit in the IN CSR register of the
corresponding endpoint. When the INTPT bit is set,
the data toggle bits will be changed after each packet
is sent to the host without regard to the presence or
type of handshake packet.
0
0
1
1
1
IN_PKT_RDY
TX_NOT_EMPTY
0
TX FIFO Status
1
0
Invalid
Two data packets in TX FIFO if MAXP <=
1/2 of the FIFO size
OR
One data packet in TX FIFO if MAXP >
1/2 of the FIFO size
No Data packet in TX FIFO
One data packet in TX FIFO if MAXP <=
1/2 of the FIFO size
Invalid if MAXP > 1/2 of the FIFO size/
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