參數(shù)資料
型號： M37548G1FP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 65/73頁
文件大小： 1255K
代理商： M37548G1FP
Rev.2.00
REJ03B0210-0200
Mar 15, 2007
Page 65 of 70
7548 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Power-on reset circuit characteristics
Power-on reset circuit characteristics
(V
CC
= 1.8 to 5.5 V, V
SS
= 0 V, Ta =
20 to 85
°
C, unless otherwise noted)
NOTE:
1. V
POR
is the start voltage level of Vcc for the built-in power-on reset circuit to operate normally.
Keep V
POR
to be lower than the Vcc voltage before rising of the Vcc power source to use the built-in power-on reset circuit.
Set the built-in low voltage detection circuit to be valid when the built-in power-on reset is used.
Low voltage detection circuit characteristics
Low voltage detection circuit characteristics
(V
CC
= 1.8 to 5.5 V, V
SS
= 0 V, Ta =
20 to 85
°
C, unless otherwise noted)
NOTE:
1. V
LVD
is the start voltage level of Vcc for the built-in low voltage detection circuit to operate normally.
If the Vcc power source becomes lower than V
LVD
, first set the Vcc voltage to be lower than V
POR
. Next, according to the electrical
characteristics of the power-on reset circuit, perform the rising of Vcc.
Fig 82. Electrical characteristics of power-on reset circuit and voltage drop detection circuit
V
POR
TW(V
POR
)
TW(V
POR
-V
DET
)
Valid start voltage of power-on reset circuit (Note)
V
POR
hold time
Rising time of valid power source of power-on reset circuit
Symbol
Parameter
Limits
Unit
Min.
Typ.
V
s
ms
Max.
0
10
20
TW(V
POR
) > 10 s
Test conditions
V
LVD
TW(V
LVD
)
TW(V
LVD
-V
DET
)
V
DET-
V(V
DET+-
V
DET-
)
T
DET
Valid start voltage of low voltage detection circuit (Note)
V
LVD
hold time
Rising time of valid power source of low voltage detection circuit
Detection voltage of low voltage detection circuit
Detection voltage Hysteresis (when hysteresis is valid)
Detection time of low 5voltage detection circuit
Symbol
Parameter
Limits
Unit
Min.
1.0
1.85
1.80
Typ.
1.95
1.95
0.10
20
V
s
s
V
V
V
μ
s
Max.
10
10
2.05
2.10
TW(V
LVD
) > 10 s
T
a
= 0
50 °C
T
a
=
20
85 °C
T
a
=
20
85 °C
Test conditions
Vcc power source
waveform
V
POR
0 V
TW(V
POR
)T
T(V
PON
-V
DET
)
T
DET
TW(V
LVD
)T
T(V
LVD
-V
DET
)
Note
V
DET+
V
DET-
Internal reset signal
Power-on reset circuit
characteristics
Low voltage detection circuit
characteristics
V
POR
Note: If schmitt of the voltage drop detection circuit is set to be invalid, system is released from reset at the timing of rising to
power source voltage V
DET-
.
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