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參數(shù)資料
| 型號(hào)： | M37548G1FP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 37/73頁 |
| 文件大小： | 1255K |
| 代理商： | M37548G1FP |
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Rev.2.00
REJ03B0210-0200
Mar 15, 2007
Page 37 of 70
7548 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A/D Converter
The functional blocks of the A/D converter are described below.
[AD conversion register] AD
The A/D conversion register is a read-only register that stores the
result of A/D conversion. Do not read out this register during an
A/D conversion.
[AD control register] ADCON
The AD control register controls the A/D converter.
Bit 2 to 0 are analog input pin selection bits.
Bit 3 is the AD conversion clock selection bit. When “0” is set to
this bit, the A/D conversion clock is
φ
SOURCE/2 and the A/D
conversion time is 122 cycles of
φ
SOURCE. When “1” is set to
this bit, the A/D conversion clock is
φ
SOURCE and the A/D
conversion time is 61 cycles of
φ
SOURCE.
Bit 4 is the AD conversion completion bit. The value of this bit
remains at “0” during A/D conversion, and changes to “1” at
completion of A/D conversion.
A/D conversion is started by setting this bit to “0”.
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
V
SS
and V
CC
by 1024, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of ports P1
5
/AN
5
to P1
0
/AN
0,
and inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input
voltage with the comparison voltage and stores its result into the
AD conversion register. When A/D conversion is completed, the
control circuit sets the AD conversion completion bit and the A/
D interrupt request bit to “1”. Because the comparator is
constructed linked to a capacitor, set
φ
SOURCE in order that the
A/D conversion clock is 250 kHz or over during A/D conversion.
Notes on A/D converter
As for AD translation accuracy, on the following operating
conditions,
accuracy may become low.
(1) When V
CC
voltage is lower than [ 3.0 V ], the accuracy at
the low temperature may become extremely low compared
with that at room temperature. When the system would be
used at low temperature, the use at V
CC
= 3.0 V or more is
recommended.
(2) When X
CIN
or the low-speed on-chip oscillator is selected as
φ
SOURCE, the A/D converter cannot be used.
Fig 48. Structure of AD control register
Fig 49. Structure of AD conversion register
AD control register
(ADCON: address 0034
16
, initial value: 10
16
)
Analog input pin selection bits
000: P1
0
/AN
0
001: P1
1
/AN
1
010: P1
2
/AN
2
011: P1
3
/AN
3
100: P1
4
/AN
4
101: P1
5
/AN
5
110: Not available
111: Not available
A/D conversion clock selection bit
0:
φ
SOURCE/2
1:
φ
SOURCE
A/D conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
b7
b0
Read 8-bit (Read only address 0035
16
)
(Address 0035
16
)
Read 10-bit (read in order address 0036
16
, 0035
16
)
b7
(Address 0036
16
)
(Address 0035
16
)
Note:
High-order 6-bit of address 0036
16
returns “0” when read.
b0
b9 b8
b7
b7
b0
b6 b5 b4 b3 b2 b1 b0
b9
b7
b0
b8 b7 b6 b5 b4 b3 b2
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| M37548G3FP#U0 | 功能描述:MCU 6K ROM 256K 20-SSOP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 標(biāo)準(zhǔn)包裝:250 系列:LPC11Uxx 核心處理器:ARM? Cortex?-M0 芯體尺寸:32-位 速度:50MHz 連通性:I²C，Microwire，SPI，SSI，SSP，UART/USART，USB 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，POR，WDT 輸入/輸出數(shù):40 程序存儲(chǔ)器容量:96KB（96K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-LQFP 包裝:托盤 其它名稱:568-9587 |
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