參數(shù)資料
型號： M37548G1FP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 27/73頁
文件大?。?/td> 1255K
代理商： M37548G1FP
Rev.2.00
REJ03B0210-0200
Mar 15, 2007
Page 27 of 70
7548 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Output compare
7548 group has 3-output compare channels. Each channel (0 to
2) has the same function and can be used to output waveform by
using count value of Timer A.
Three output compare channels share the registers with the input
capture (one channel), but their individual circuits operate
independently so that all the channels can be used at the same
time.
To use each compare channel, set “1” to the compare x (x = 0, 1,
2, 3) output port bit and set the port direction register
corresponding to compare channel to output mode.
The compare value for each channel is set to the capture/compare
register (low-order) and capture/compare register (high-order).
Writing to the register for each channel is controlled by setting
value of capture/compare register RW pointer. Writing to each
register is in the following order;
1.Set the corresponding compare latch to the capture/compare
register RW pointer.
2.Write a value to the capture/compare register (low-order)
and capture/compare register (high-order). (It doesn’t care
even if either low-order or high-order is written early.)
3.Set “1” to the compare latch y (y = 00, 01, 10, 11, 20, 21)
re-load bit.
When “1” is set to the compare latch y re-load bit, the value set to
the compare register is loaded to compare latch when the next
timer underflow.
After loading, re-load bit is set to “0” automatically.
When the count value of timer A matches the compare latch
setting value, a trigger to the compare output circuit is generated.
The trigger can be enabled or disabled using the compare x
trigger enable bit. When the compare x trigger enable bit is set to
1, the output waveform from the port is as follows.
When the value of the compare x output level latch is “0”
High level at compare latch x0 match
Low level at compare latch x1 match
When the value of the compare x output level latch is “1”
Low level at compare latch x0 match
High level at compare latch x1 match
The output waveform does not change if the compare x trigger
enable bit is set to 0, so the port output remains fixed at high or
low level.
The compare output level of each channel can be confirmed by
reading the compare x output status bit.
Compare interrupt is available when match of each compare
channel and timer count value. The interrupt request from each
channel can be disabled or enabled by setting value of compare
latch y interrupt source selection bit.
Notes on Output Compare
(1) If timer A is stopped, when a value is written to the capture/
compare register it is immediately transferred to the
compare latch. In addition, if timer A is stopped and the
compare x trigger enable bit is set to “1”, the output latch is
initialized.
(2) Do not write the same data to both of compare latch x0 and
x1.
(3) When setting value of the compare latch is larger than timer
setting value, compare match signal is not generated.
Accordingly, the output waveform is fixed to “L” or “H”
level.
However, when setting value of another compare latch is
smaller than timer setting value, this compare match signal
is generated. Accordingly, compare interrupt occurs.
(4) When the compare x trigger enable bit is cleared to “0”
(disabled), the match trigger to the waveform output circuit
is disabled, and the output waveform can be fixed to “L” or
“H” level.
However, in this case, the compare match signal is
generated.
Accordingly, compare interrupt occurs.
Fig 27. Structure of capture/compare register
Fig 28. Structure of capture/compare register RW
pointer
Fig 29. Structure of compare register re-load register
Fig 30. Structure of capture/compare port register
b7
b0
Capture/Compare register (low-order)
(CRAL: address 0010
16
, initial value: 00
16
)
b7
b0
Capture/Compare register (high-order)
16
, initial value: 00
16
)
b7
b0
Capture/Compare register RW pointer
16
, initial value: 00
16
)
Cb2 b1 b0
0 0 0 : Compare latch 00
Not used (returns “0” when read)
b7
b0
Compare register re-load register
16
, initial value: 00
16
)
Compare latch 00, 01 re-load bit
Compare latch 10, 11 re-load bit
Compare latch 20, 21 re-load bit
Not used (returns “0” when read)
b7
b0
Capture/Compare port register
16
, initial value: 00
16
)
C0: Capture from P0
1: Low-speed on-chip oscillator/16
C0: P1
0
1: P1
0
is I/O port
C0: P1
1
1: P1
1
is I/O port
C0: P1
2
1: P1
2
is I/O port
Not used (returns “0” when read)
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