參數(shù)資料
型號(hào)： M37544G2ASP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝： 28 X 8.90 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁(yè)數(shù)： 71/75頁(yè)
文件大?。?/td> 649K
代理商： M37544G2ASP
1.02 Jul 20, 2005 All pages Delete the following: "PRELIMINARY".
2, 4, 5, 7 Package names are revised.
3Table 1 Performance overview is added.
7
Table 2 is deleted.
12
ROM code protect is added.
Fig.10 is partly revised.
18
Termination of unused pins is added.
41
(4)Wiring to CNVSS pin is deleted.
(4)Wiring to VPP pin is revised.
Fig.49 is partly revised.
45
Table 8 is partly revised.
53
PACKAGE OUTLINE is revised.
61
Product shipped in blank, NOTES ON QzROM, DATA REQUIRED FOR QzROM
WRITING ORDERS are added.
1.03 Mar 31, 2009
3,8
42S1M package added
13
Fig. 11 Memory map diagram revised
17
Fig. 15 (5)Port P11 revised
18
Fig. 16 (8)Port P14 revised
19
Table 7 XIN, XOUT added
20-25
“Interrupts” revised
36, 70, 71 Operation of STP instruction disable bit
→ Operation of STP instruction function selection bit
36
Watchdog Timer
“Operation of watchdog timer H count source selection bit” revised
“Operation of STP instruction function selection bit” revised
“Notes on watchdog timer” added
37
-Fig. 36 Block diagram of watchdog timer revised
-Fig. 37 Structure of watchdog timer control register revised
41
“-Clock division ratio, XIN oscillation control, on-chip oscillator control” added
45-49
“QzROM Writing Mode”added
50
“Processor Status Register”revised
51
Fig. 57 VPP → CNVSS
54
5. Setup for I/O ports “Note” deleted
55
“NOTES ON QzROM” added
65
-“1. Processor Status Register”revised
APPENDIX “Fig. 2 Sequence of PLP Instruction execution deleted.
-Figure title of Fig. 3 revised
66
“3. Modifying output data with bit managing instruction” revised
70
Notes on A/D conversion 1. Analog input pin revised
Notes on Watchdog Timer revised
REVISION HISTORY
Rev.
Date
Description
Page
Summary
(1/2)
7544 Group (QzROM version) Data Sheet
1.00 Oct 26, 2004
1.01 Nov 24, 2004
First edition issued
Table 12 Electrical characteristics: Minimum value of VRAM revised.
The followings are added;
- A/D Converter characteristics
- Timing requirements
- Switching Characteristics
- Timing chart
–
46
48-50
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