參數(shù)資料
型號(hào)： M37544G2ASP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝： 28 X 8.90 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁(yè)數(shù)： 30/75頁(yè)
文件大?。?/td> 649K
代理商： M37544G2ASP
7544 Group (QzROM version)
REJ03B0108-0103
Rev.1.03
Mar 31, 2009
page 36 of 72
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control regis-
ter (address 003916) is not set after reset. Writing an optional
value to the watchdog timer control register (address 003916)
causes the watchdog timer to start to count down. When the
watchdog timer H underflows, an internal reset occurs. Accord-
ingly, it is programmed that the watchdog timer control register
(address 003916) can be set before an underflow occurs.
When the watchdog timer control register (address 003916) is
read, the values of the high-order 6-bit of the watchdog timer H,
STP instruction function selection bit and watchdog timer H count
source selection bit are read.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (ad-
dress 003916), the watchdog timer H is set to “FF16” and the
watchdog timer L is set to “FF16”.
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 003916). When this bit is
“0”, the count source becomes a watchdog timer L underflow sig-
nal. The detection time is 131.072 ms at f(XIN)=8 MHz.
When this bit is “1”, the count source becomes f(XIN)/16 or on-chip
oscillator/16. In this case, the detection time is 512 s at f(XIN)=8
MHz.
This bit is cleared to “0” after reset.
Operation of STP instruction function selection bit
The function of the STP instruction can be set by the STP instruc-
tion function selection bit (bit 6 of WDTCON).
When “0” is set to this bit, system enters into the stop mode at the
STP instruction execution.
When “1” is set to this bit, internal reset occurs at the STP instruc-
tion execution.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
■ Notes on watchdog timer
1. The watchdog timer is operating during the wait mode. Write
data to the watchdog timer control register to prevent timer un-
derflow.
2. The watchdog timer stops during the stop mode. However, the
watchdog timer is running during the oscillation stabilizing time
after the STP instruction is released. In order to avoid the un-
derflow of the watchdog timer, the watchdog timer count source
selection bit (bit 7 of watchdog timer control register (address
003916)) before executing the STP instruction.
3. The STP instruction function selection bit (bit 6 of watchdog
timer control register (address 003916)) can be rewritten only
once after releasing reset. After rewriting it is disable to write
any data to this bit.
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